公开(公告)号：US12051681B2

公开(公告)日：2024-07-30

申请号：US17374868

申请日：2021-07-13

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS ,  STMICROELECTRONICS (ALPS) SAS

Inventor： Deborah Cogoni ,  David Auchere ,  Laurent Schwartz ,  Claire Laporte

IPC: H01L25/16 ,  H01G4/38

CPC classification number: H01L25/165 ,  H01G4/385

Abstract: A device for regulating a voltage of an electric current supplying an integrated circuit resting on a substrate. The integrated circuit comprises a ground terminal and a power supply terminal able to receive the electric current. The regulation device comprises a first cover covering the integrated circuit, a second cover covering the integrated circuit. The first cover is electrically connected to the power supply terminal of the integrated circuit. The second cover is electrically connected to the ground terminal of the integrated circuit. The first cover and the second cover are connected together by a capacitive connection.

公开(公告)号：US11756874B2

公开(公告)日：2023-09-12

申请号：US17945822

申请日：2022-09-15

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： David Auchere ,  Claire Laporte ,  Deborah Cogoni ,  Laurent Schwartz

IPC: H01L23/50 ,  H01L23/31

CPC classification number: H01L23/50 ,  H01L23/315 ,  H01L23/3128

Abstract: An electronic device includes a carrier substrate with an electronic IC chip mounted on top of the carrier substrate. An encapsulation block on top of the front face of the carrier substrate embeds the IC chip. The encapsulation block has a through-void for positioning and confinement that extends through the encapsulation block to the top of the carrier substrate. At least one electronic component is positioned within the through-void and mounted to the top of the carrier substrate. Solder bumps or pads are located within the through-void to electrically connect the at least one electronic component to the carrier substrate.

公开(公告)号：US11888208B2

公开(公告)日：2024-01-30

申请号：US17408982

申请日：2021-08-23

Applicant: STMicroelectronics (Alps) SAS

Inventor： Deborah Cogoni

IPC: H01Q9/04 ,  H01Q1/12 ,  H01Q1/38

CPC classification number: H01Q1/12 ,  H01Q1/38

Abstract: An electronic device includes a first layer with an antenna and a second metal layer that extends over the entire first layer. The second metal layer includes at least one laterally-closed cavity that is located vertically above the antenna. The cavity is filled, at least in part, by a resin material. A first plate supporting a second metal plate extends over the cavity with the second metal plate positioned vertically above the antenna. The first metal plate may be supported by a ledge within the cavity. Alternatively, the second metal plate is embedded in the resin filling the cavity, with the second metal plate positioned vertically above the antenna.

公开(公告)号：US11482487B2

公开(公告)日：2022-10-25

申请号：US17064119

申请日：2020-10-06

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： David Auchere ,  Claire Laporte ,  Deborah Cogoni ,  Laurent Schwartz

IPC: H01L23/50 ,  H01L23/31

Abstract: An electronic device includes a carrier substrate with an electronic IC chip mounted on top of the carrier substrate. An encapsulation block on top of the front face of the carrier substrate embeds the IC chip. The encapsulation block has a through-void for positioning and confinement that extends through the encapsulation block to the top of the carrier substrate. At least one electronic component is positioned within the through-void and mounted to the top of the carrier substrate. Solder bumps or pads are located within the through-void to electrically connect the at least one electronic component to the carrier substrate.

公开(公告)号：US10811349B2

公开(公告)日：2020-10-20

申请号：US16110121

申请日：2018-08-23

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： David Auchere ,  Laurent Schwarz ,  Deborah Cogoni ,  Eric Saugier

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H05K1/18 ,  H01L23/31 ,  H01L23/13 ,  H01L21/56 ,  H01L21/78

Abstract: An electronic device includes a support wafer, an electronic chip and an encapsulating block for the electronic chip above the support wafer. The support wafer is provided with a first network of electrical connections and a second network of electrical connections formed solely by tracks. First electrical connection elements are interposed between first front electrical contacts of the electronic chip and rear electrical contacts of the first network. Second electrical connection elements are interposed between second front electrical contacts of the electronic chip and internal electrical contact zones of the tracks of the second network. The first network includes front external electrical contacts and the tracks exhibiting external electrical contact zones.