公开(公告)号：US20180090389A1

公开(公告)日：2018-03-29

申请号：US15458109

申请日：2017-03-14

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Guillaume C. Ribes ,  Benjamin Dumont ,  Franck Arnaud

IPC: H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51 ,  H01L21/84

CPC classification number: H01L21/823842 ,  H01L21/82345 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/42372 ,  H01L29/42384 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/7838

Abstract: An integrated circuit includes FDSOI-type MOS transistors formed inside and on top of a semiconductor layer resting on an insulating layer. The transistors include a logic MOS transistor of a first conductivity type, a logic MOS transistor of a second conductivity type, and an analog MOS transistor of the first conductivity type, A gate stack of the logic transistors successively includes a gate insulator layer, a first titanium nitride layer, a lanthanum layer, and a second titanium nitride layer. A gate stack of the analog transistor includes the gate insulator layer, the lanthanum layer and the second titanium nitride layer but not the first titanium nitride layer.