公开(公告)号：US11171034B2

公开(公告)日：2021-11-09

申请号：US16707614

申请日：2019-12-09

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Pascal Gouraud ,  Delia Ristoiu

IPC: H01L21/00 ,  H01L21/762 ,  H01L29/06

Abstract: A substrate includes a first solid semiconductor region and a second semiconductor on insulator region. First and second cavities are simultaneously formed in the first and second regions, respectively, of the substrate using etching processes in two steps which form an upper portion and a lower portion of each cavity. The first and second cavities will each have a step at a level of an upper surface of the insulator of the second semiconductor on insulator region. A further oxidation of the first cavity produces a rounded or cut-off area for the upper portion.

公开(公告)号：US10304775B2

公开(公告)日：2019-05-28

申请号：US15700960

申请日：2017-09-11

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Philippe Boivin ,  Delia Ristoiu

IPC: H01L23/535 ,  H01L23/48 ,  H01L21/768 ,  H01L23/485 ,  H01L27/12 ,  H01L23/532

Abstract: A connecting bar electrically connects separate circuit zones of an integrated circuit. The connecting bar is formed by a main portion that is a conductive strip extending above separate circuit zones to be interconnected. The conductive strip is separated from the integrated circuit by a dielectric except at the circuit zones to be interconnected. The connecting bar further includes secondary portions that are conductive pads passing through the dielectric in a vertical direction from the circuit zone to the conductive strip.

公开(公告)号：US10128295B2

公开(公告)日：2018-11-13

申请号：US15866995

申请日：2018-01-10

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sebastien Lagrasta ,  Delia Ristoiu ,  Jean-Pierre Oddou ,  Cécile Jenny

IPC: H01L27/146

Abstract: A semiconductor substrate includes a photodiode region, a charge storage region electrically coupled to the photodiode region and a capacitive deep trench isolation (CDTI) structure including a conductive region positioned between the photodiode region and the charge storage region. A contact etch stop layer overlies the semiconductor substrate and a premetallization dielectric layer overlies the contact etch stop layer. A first trench, filled with a metal material, extends through the premetallization dielectric layer and bottoms out at or in the contact etch stop layer. A second trench, also filled with the metal material, extends through the premetallization dielectric layer and the contact etch stop layer and bottoms out at or in the conductive region of the CDTI structure. The metal filled first trench forms an optical shield between the photodiode region and the charge storage region. The metal filled second trench forms a contact for biasing the CDTI structure.

公开(公告)号：US20180211915A1

公开(公告)日：2018-07-26

申请号：US15700960

申请日：2017-09-11

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Philippe Boivin ,  Delia Ristoiu

IPC: H01L23/535 ,  H01L23/532 ,  H01L21/768 ,  H01L27/12

CPC classification number: H01L23/535 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76879 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/53257 ,  H01L27/1203

Abstract: A connecting bar electrically connects separate circuit zones of an integrated circuit. The connecting bar is formed by a main portion that is a conductive strip extending above separate circuit zones to be interconnected. The conductive strip is separated from the integrated circuit by a dielectric except at the circuit zones to be interconnected. The connecting bar further includes secondary portions that are conductive pads passing through the dielectric in a vertical direction from the circuit zone to the conductive strip.

公开(公告)号：US11901216B2

公开(公告)日：2024-02-13

申请号：US17496411

申请日：2021-10-07

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Pascal Gouraud ,  Delia Ristoiu

IPC: H01L21/00 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L21/7621 ,  H01L29/0649

Abstract: A substrate includes a first solid semiconductor region and a second semiconductor on insulator region. First and second cavities are simultaneously formed in the first and second regions, respectively, of the substrate using etching processes in two steps which form an upper portion and a lower portion of each cavity. The first and second cavities will each have a step at a level of an upper surface of the insulator of the second semiconductor on insulator region. A further oxidation of the first cavity produces a rounded or cut-off area for the upper portion.

公开(公告)号：US20180076250A1

公开(公告)日：2018-03-15

申请号：US15263922

申请日：2016-09-13

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sebastien Lagrasta ,  Delia Ristoiu ,  Jean-Pierre Oddou ,  Cécile Jenny

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14623 ,  H01L27/1463 ,  H01L27/14641 ,  H01L27/14654 ,  H01L27/14685 ,  H01L27/14689

Abstract: A semiconductor substrate includes a photodiode region, a charge storage region electrically coupled to the photodiode region and a capacitive deep trench isolation (CDTI) structure including a conductive region positioned between the photodiode region and the charge storage region. A contact etch stop layer overlies the semiconductor substrate and a premetallization dielectric layer overlies the contact etch stop layer. A first trench, filled with a metal material, extends through the premetallization dielectric layer and bottoms out at or in the contact etch stop layer. A second trench, also filled with the metal material, extends through the premetallization dielectric layer and the contact etch stop layer and bottoms out at or in the conductive region of the CDTI structure. The metal filled first trench forms an optical shield between the photodiode region and the charge storage region. The metal filled second trench forms a contact for biasing the CDTI structure.

公开(公告)号：US11469095B2

公开(公告)日：2022-10-11

申请号：US16709251

申请日：2019-12-10

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Delia Ristoiu ,  Pierre Bar ,  Francois Leverd

IPC: H01L21/311 ,  H01L21/02 ,  H01L21/67

Abstract: The present disclosure relates to a method for forming a cavity that traverses a stack of layers including a bottom layer, a first portion of which locally presents an excess thickness, the method comprising a first step of non-selective etching and a second step of selective etching vertically in line with the first portion.

公开(公告)号：US10770306B2

公开(公告)日：2020-09-08

申请号：US16240044

申请日：2019-01-04

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Pierre Bar ,  Francois Leverd ,  Delia Ristoiu

IPC: H01L21/3065 ,  H01L21/311 ,  H01L21/308 ,  H01L21/02 ,  G02B6/36 ,  G02B6/42

Abstract: A cavity is etched in a stack of layers which includes a first layer made of a first material and a second layer made of a second material. To etch the cavity, a first etch mask having a first opening is formed over the stack of layer. The stack of layers is then etched through the first opening to a depth located in the second layer. A second mask having a second opening, the dimensions of which are smaller, in top view, than the first opening, is formed over the stack of layer. The second opening is located, in top view, opposite the area etched through the first opening. The second layer is then etched through the second opening to reach the first layer. The etch method used is configured to etch the second material selectively over the first material.

公开(公告)号：US20180158861A1

公开(公告)日：2018-06-07

申请号：US15866995

申请日：2018-01-10

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sebastien Lagrasta ,  Delia Ristoiu ,  Jean-Pierre Oddou ,  Cécile Jenny

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14623 ,  H01L27/1463 ,  H01L27/14641 ,  H01L27/14654 ,  H01L27/14685 ,  H01L27/14689

Abstract: A semiconductor substrate includes a photodiode region, a charge storage region electrically coupled to the photodiode region and a capacitive deep trench isolation (CDTI) structure including a conductive region positioned between the photodiode region and the charge storage region. A contact etch stop layer overlies the semiconductor substrate and a premetallization dielectric layer overlies the contact etch stop layer. A first trench, filled with a metal material, extends through the premetallization dielectric layer and bottoms out at or in the contact etch stop layer. A second trench, also filled with the metal material, extends through the premetallization dielectric layer and the contact etch stop layer and bottoms out at or in the conductive region of the CDTI structure. The metal filled first trench forms an optical shield between the photodiode region and the charge storage region. The metal filled second trench forms a contact for biasing the CDTI structure.

公开(公告)号：US09917126B1

公开(公告)日：2018-03-13

申请号：US15263922

申请日：2016-09-13

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sebastien Lagrasta ,  Delia Ristoiu ,  Jean-Pierre Oddou ,  Cécile Jenny

IPC: H01L31/062 ,  H01L31/113 ,  H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14623 ,  H01L27/1463 ,  H01L27/14641 ,  H01L27/14654 ,  H01L27/14685 ,  H01L27/14689

Abstract: A semiconductor substrate includes a photodiode region, a charge storage region electrically coupled to the photodiode region and a capacitive deep trench isolation (CDTI) structure including a conductive region positioned between the photodiode region and the charge storage region. A contact etch stop layer overlies the semiconductor substrate and a premetallization dielectric layer overlies the contact etch stop layer. A first trench, filled with a metal material, extends through the premetallization dielectric layer and bottoms out at or in the contact etch stop layer. A second trench, also filled with the metal material, extends through the premetallization dielectric layer and the contact etch stop layer and bottoms out at or in the conductive region of the CDTI structure. The metal filled first trench forms an optical shield between the photodiode region and the charge storage region. The metal filled second trench forms a contact for biasing the CDTI structure.