公开(公告)号：US20190386142A1

公开(公告)日：2019-12-19

申请号：US16437067

申请日：2019-06-11

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Mickael GROS-JEAN ,  Julien FERRAND

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28 ,  H01L27/07

Abstract: A ferroelectric field effect transistor includes a semiconductor substrate, with first and second source/drain regions being formed within the semiconductor substrate and being separated by a channel region. An interface layer is disposed on the channel region. A gate insulator layer is disposed on the interface layer. A ferroelectric layer is disposed on the gate insulator layer.

公开(公告)号：US20210280721A1

公开(公告)日：2021-09-09

申请号：US17323545

申请日：2021-05-18

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Mickael GROS-JEAN ,  Julien FERRAND

IPC: H01L29/78 ,  H01L21/28 ,  H01L27/07 ,  H01L29/51 ,  H01L29/66

Abstract: A method for manufacturing first and second transistors on a semiconductor substrate includes: depositing an interface layer on the semiconductor substrate; depositing a gate insulator layer on the interface layer; depositing a first ferroelectric layer on the gate insulator layer over a first region for the first transistor; depositing a metal gate layer on the gate insulator layer over a second region for the second transistor and on the first ferroelectric layer over the first region for the first transistor; and patterning the metal gate layer, first ferroelectric layer, gate insulator layer and interface layer to form a first gate stack for the first transistor which includes the metal gate layer, first ferroelectric layer, gate insulator layer and interface layer and a second gate stack for the second transistor which includes the metal gate layer, gate insulator layer and interface layer.

公开(公告)号：US20150117128A1

公开(公告)日：2015-04-30

申请号：US14527166

申请日：2014-10-29

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Pierre CAUBET ,  Mickael GROS-JEAN

IPC: G11C11/42 ,  G02F1/15 ,  H01L31/0224

CPC classification number: G11C11/42 ,  G02F1/15 ,  G02F1/1523 ,  G02F1/1525 ,  G02F1/1527 ,  G02F1/163 ,  G02F3/022 ,  G02F2001/1512 ,  G02F2001/1635 ,  G02F2201/58 ,  G11C7/00 ,  G11C13/04

Abstract: A memory device may include an access transistor, and a memory cell configured to store an item of information. The memory cell may include first and second electrodes configured to have different optoelectronic states corresponding respectively to two values of the item of information, and to switch between the different optoelectronic states based upon a control signal external to the memory cell, the different optoelectronic states being naturally stable in an absence of the control signal. The memory cell may also include a solid electrolyte between the first and second electrodes.

Abstract translation: 存储器件可以包括存取晶体管，以及被配置为存储信息项的存储单元。 存储单元可以包括被配置为具有分别对应于信息项的两个值的不同光电子状态的第一和第二电极，以及基于存储单元外部的控制信号在不同的光电子态之间切换，不同的光电子态是 在没有控制信号的情况下自然稳定。 存储单元还可以包括在第一和第二电极之间的固体电解质。