公开(公告)号：US09165883B2

公开(公告)日：2015-10-20

申请号：US14257543

申请日：2014-04-21

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Patrick Vannier

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/4763 ,  H01L21/44 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The disclosure relates to a method of fabricating an interconnection structure of an integrated circuit, comprising the steps of: forming a first conductive element within a first dielectric layer; depositing a first etch stop layer above the first conductive element and the first dielectric layer; forming an opening in the first etch stop layer above the first conductive element, to form a first connection area; depositing a second dielectric layer above the etch stop layer and above the first conductive element in the connection area; etching the second dielectric layer to form at least one hole which is at least partially aligned with the connection area; and filling the hole with a conductive material to form a second conductive element in electrical contact with the first conductive element.

Abstract translation: 本公开涉及一种制造集成电路的互连结构的方法，包括以下步骤：在第一介电层内形成第一导电元件; 在所述第一导电元件和所述第一介电层上沉积第一蚀刻停止层; 在所述第一导电元件上方的所述第一蚀刻停止层中形成开口，以形成第一连接区域; 在所述连接区域中沉积在所述蚀刻停止层上方和所述第一导电元件上方的第二电介质层; 蚀刻所述第二电介质层以形成至少一个至少部分地与所述连接区域对齐的孔; 以及用导电材料填充所述孔，以形成与所述第一导电元件电接触的第二导电元件。

公开(公告)号：US20140225278A1

公开(公告)日：2014-08-14

申请号：US14257543

申请日：2014-04-21

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Patrick Vannier

IPC: H01L23/522

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The disclosure relates to a method of fabricating an interconnection structure of an integrated circuit, comprising the steps of: forming a first conductive element within a first dielectric layer; depositing a first etch stop layer above the first conductive element and the first dielectric layer; forming an opening in the first etch stop layer above the first conductive element, to form a first connection area; depositing a second dielectric layer above the etch stop layer and above the first conductive element in the connection area; etching the second dielectric layer to form at least one hole which is at least partially aligned with the connection area; and filling the hole with a conductive material to form a second conductive element in electrical contact with the first conductive element.

Abstract translation: 本公开涉及一种制造集成电路的互连结构的方法，包括以下步骤：在第一介电层内形成第一导电元件; 在所述第一导电元件和所述第一介电层上沉积第一蚀刻停止层; 在所述第一导电元件上方的所述第一蚀刻停止层中形成开口，以形成第一连接区域; 在所述连接区域中沉积在所述蚀刻停止层上方和所述第一导电元件上方的第二电介质层; 蚀刻所述第二电介质层以形成至少一个至少部分地与所述连接区域对齐的孔; 以及用导电材料填充所述孔，以形成与所述第一导电元件电接触的第二导电元件。