公开(公告)号：US20140292374A1

公开(公告)日：2014-10-02

申请号：US14225520

申请日：2014-03-26

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Bastien Giraud ,  Fady Abouzeid ,  Sylvain Clerc ,  Jean-Philippe Noel ,  Philippe Roche ,  Yvain Thonnart

IPC: H03K19/00 ,  H03K19/0185

CPC classification number: H03K19/0016 ,  H01L27/0928 ,  H01L27/11807 ,  H01L27/1203 ,  H03K19/0013 ,  H03K19/01855 ,  H03K2217/0018

Abstract: A method for controlling an IC having logic cells and a clock-tree cell. Each logic cell has first and second FETs, which are pMOS and nMOS respectively. The clock-tree cell includes third and fourth FETs, which are pMOS and nMOS respectively. The clock-tree cell provides a clock signal to the logic cells. A back gate potential difference (“BGPD”) of a pMOS-FET is a difference between its source potential less its back-gate potential, and vice versa for an nMOS-FET. The method includes applying first and second back gate potential difference (BGPD) to a logic cell's first and second FETs and either applying a third BGPD to a third FET, wherein the third BGPD is positive and greater than the first BGPD applied, which is applied concurrently, or applying a fourth BGEPD to a fourth FET, wherein the fourth BGPD is positive and greater than the second BGPD that is applied concurrently.

Abstract translation: 一种用于控制具有逻辑单元和时钟树单元的IC的方法。 每个逻辑单元分别具有第一和第二FET，分别是pMOS和nMOS。 时钟树单元包括分别为pMOS和nMOS的第三和第四FET。 时钟树单元为逻辑单元提供时钟信号。 pMOS-FET的背栅电位差（“BGPD”）是其源电位减去其背栅电位之间的差异，反之亦然是nMOS-FET。 该方法包括将第一和第二后门电位差（BGPD）应用于逻辑单元的第一和第二FET，以及将第三BGPD应用于第三FET，其中第三BGPD为正并且大于施加的第一BGPD，其被应用 同时或将第四BGEPD应用于第四FET，其中第四BGPD为正并且大于并发应用的第二BGPD。

公开(公告)号：US10771048B2

公开(公告)日：2020-09-08

申请号：US16747341

申请日：2020-01-20

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Capucine Lecat-Mathieu De Boissac ,  Fady Abouzeid ,  Gilles Gasiot ,  Philippe Roche ,  Victor Malherbe

IPC: H03K5/14 ,  H03K5/135 ,  H03K5/00

Abstract: A first circuit includes a first chain of identical stages defining first and second delay lines. A second circuit includes a second chain of identical stages defining third and fourth delay lines. The stages of the second chain are identical to the stages of the first chain. A third circuit selectively couples one of the third delay line, the fourth delay line, or a first input of the third circuit to an input of the first circuit.

公开(公告)号：US09479168B2

公开(公告)日：2016-10-25

申请号：US14225520

申请日：2014-03-26

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Bastien Giraud ,  Fady Abouzeid ,  Sylvain Clerc ,  Jean-Philippe Noel ,  Philippe Roche ,  Yvain Thonnart

IPC: H03K19/096 ,  H03K19/00 ,  H01L27/092 ,  H01L27/118 ,  H01L27/12 ,  H03K19/0185

CPC classification number: H03K19/0016 ,  H01L27/0928 ,  H01L27/11807 ,  H01L27/1203 ,  H03K19/0013 ,  H03K19/01855 ,  H03K2217/0018

Abstract: A method for controlling an IC having logic cells and a clock-tree cell. Each logic cell has first and second FETs, which are pMOS and nMOS respectively. The clock-tree cell includes third and fourth FETs, which are pMOS and nMOS respectively. The clock-tree cell provides a clock signal to the logic cells. A back gate potential difference (“BGPD”) of a pMOS-FET is a difference between its source potential less its back-gate potential, and vice versa for an nMOS-FET. The method includes applying first and second back gate potential difference (BGPD) to a logic cell's first and second FETs and either applying a third BGPD to a third FET, wherein the third BGPD is positive and greater than the first BGPD applied, which is applied concurrently, or applying a fourth BGEPD to a fourth FET, wherein the fourth BGPD is positive and greater than the second BGPD that is applied concurrently.

Abstract translation: 一种用于控制具有逻辑单元和时钟树单元的IC的方法。 每个逻辑单元分别具有第一和第二FET，分别是pMOS和nMOS。 时钟树单元包括分别为pMOS和nMOS的第三和第四FET。 时钟树单元为逻辑单元提供时钟信号。 pMOS-FET的背栅电位差（“BGPD”）是其源电位减去其背栅电位之间的差异，反之亦然是nMOS-FET。 该方法包括将第一和第二后门电位差（BGPD）应用于逻辑单元的第一和第二FET，以及将第三BGPD应用于第三FET，其中第三BGPD为正并且大于施加的第一BGPD，其被应用 同时或将第四BGEPD应用于第四FET，其中第四BGPD为正并且大于并发应用的第二BGPD。

公开(公告)号：US10948611B2

公开(公告)日：2021-03-16

申请号：US15981321

申请日：2018-05-16

Applicant: STMicroelectronics (Crolles 2) SAS ,  Centre National De La Recherche Scientifique ,  UNIVERSITE D'AIX MARSEILLE ,  UNIVERSITE DE TOULON

Inventor： Martin Cochet ,  Dimitri Soussan ,  Fady Abouzeid ,  Gilles Gasiot ,  Philippe Roche

IPC: G01T1/02 ,  H03K3/03

Abstract: Absorbed ionizing particles differentially effect first and second acquiring circuit stages configured to respectively generate first and second acquisition signals. Each acquisition signal has a characteristic that is variable as a function of an amount of absorbed ionizing particles. A measuring circuit generates, on the basis of the first and second acquisition signals, a relative parameter indicative of a relationship between the variable characteristics. A computation of a total ionizing dose is made using a 1st- or 2nd-degree polynomial relationship in the relative parameter.

公开(公告)号：US10386414B2

公开(公告)日：2019-08-20

申请号：US15324851

申请日：2015-05-28

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Jean-Marc Daveau ,  Philippe Roche ,  Didier Fuin

IPC: G01R31/3185 ,  G01R31/3177 ,  G01R31/317

Abstract: A device may include a control circuit configured to place, after a normal mode operation of N flip-flops, the N flip-flops in a test mode in which the test input of the first flip-flop of the chain is intended to receive a first sequence of test bits A memory may be configured to store a sequence of N values delivered by the test output of the last flip-flop of the chain. The control circuit may be configured to deliver, at the test input of the first flip-flop of the chain, the sequence of N stored values to restore the state of the N flip-flops before their placement in the test mode.

公开(公告)号：US09417282B2

公开(公告)日：2016-08-16

申请号：US14662530

申请日：2015-03-19

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Jean-Marc Daveau ,  Sylvain Clerc ,  Philippe Roche

IPC: G06F11/08 ,  G01R31/3177 ,  G06F11/267 ,  G01R31/3185 ,  G06F11/18

CPC classification number: G01R31/3177 ,  G01R31/318502 ,  G06F11/183 ,  G06F11/267

Abstract: A method for managing operation of a logic component is provided, with the logic component including a majority vote circuit and an odd number of flip-flops equal to at least three. The method includes, following a normal operating mode of the logic component, placing a flip-flop in a test mode, and injecting a test signal into a test input of the flip-flop being tested while a logic state of the other flip-flops is frozen. A test signal output is analyzed. At the end of the test, the logic component is placed back in the normal operating mode. The majority vote circuit restores a value of the output signal from the logic component that existed prior to initiation of the test.

Abstract translation: 提供了一种用于管理逻辑部件的操作的方法，其中逻辑部件包括等于至少三个的多数投票电路和奇数触发器。 该方法包括：遵循逻辑部件的正常操作模式，将触发器置于测试模式，并将测试信号注入被测试的触发器的测试输入，而其它触发器的逻辑状态 被冻结。 分析测试信号输出。 在测试结束时，将逻辑组件放回正常操作模式。 多数投票电路恢复来自在开始测试之前存在的逻辑组件的输出信号的值。