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公开(公告)号:US20170192053A1
公开(公告)日:2017-07-06
申请号:US14986053
申请日:2015-12-31
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor: David Jacquet , Didier Fuin
IPC: G01R31/3177 , G01R31/317
CPC classification number: G01R31/3177 , G01R31/31703 , G01R31/31708 , G01R31/318566 , G01R31/318569
Abstract: A digital circuit includes a scan chain which loads data into and unloads data from the digital circuit. Checking circuitry is coupled to the scan chain and generates a first digital signature based on data indicative of a pre-testing status of the digital circuit as the data is unloaded from the digital circuit via the scan chain. When testing is completed, the data is restored to the digital circuit via the scan chain. The checking circuitry generates a second digital signature as the data is loaded into the digital circuit. The first digital signature is compared to the second digital signature to verify an integrity of the process. A specific data pattern may be loaded into the scan chain as the data is unloaded. An output of the scan chain may be monitored to detect the pattern and an error signal may be generated based on when the pattern is detected.
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公开(公告)号:US11271570B1
公开(公告)日:2022-03-08
申请号:US16951748
申请日:2020-11-18
Inventor: Marc Gens , David Jacquet , Fabien Pousset , Elias El Haddad
Abstract: The system comprising a slave module and a master module. The master module comprises a master control module (CONTRM). The slave module comprises a determination module (DETER). The determination module (DETER) is configured to determine a value of a physical quantity of the slave module. The determination module (DETER) is configured to receive, from the master control module (CONTRM), a command to start counting and a command to end counting. The determination module (DETER) is configured to determine a number of oscillations, between reception of the command to start counting and reception of the command to end counting, of an oscillating signal of which a frequency depends on the value of the physical quantity.
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公开(公告)号:US10578672B2
公开(公告)日:2020-03-03
申请号:US14986053
申请日:2015-12-31
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor: David Jacquet , Didier Fuin
IPC: G01R31/317 , G01R31/3177 , G01R31/3185
Abstract: A digital circuit includes a scan chain which loads data into and unloads data from the digital circuit. Checking circuitry is coupled to the scan chain and generates a first digital signature based on data indicative of a pre-testing status of the digital circuit as the data is unloaded from the digital circuit via the scan chain. When testing is completed, the data is restored to the digital circuit via the scan chain. The checking circuitry generates a second digital signature as the data is loaded into the digital circuit. The first digital signature is compared to the second digital signature to verify an integrity of the process. A specific data pattern may be loaded into the scan chain as the data is unloaded. An output of the scan chain may be monitored to detect the pattern and an error signal may be generated based on when the pattern is detected.
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