公开(公告)号：US20210367619A1

公开(公告)日：2021-11-25

申请号：US17394118

申请日：2021-08-04

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Fabrice ROMAIN ,  Mathieu LISART ,  Patrick ARNOULD

IPC: H03M13/29 ,  G06F11/10

Abstract: A datum is written to a memory, by splitting a binary word, representative of the datum and an error correcting or detecting code, into a first part and a second part. The first part is written at a logical address in a first memory circuit. The second part is written at the logical address in a second memory circuit. The error correcting or detecting code is dependent on both the datum and the logical address.

公开(公告)号：US20210067177A1

公开(公告)日：2021-03-04

申请号：US17010351

申请日：2020-09-02

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Fabrice ROMAIN ,  Mathieu LISART ,  Patrick Arnould

IPC: H03M13/29 ,  G06F11/10

Abstract: A datum is written to a memory, by splitting a binary word, representative of the datum and an error correcting or detecting code, into a first part and a second part. The first part is written at a logical address in a first memory circuit. The second part is written at the logical address in a second memory circuit. The error correcting or detecting code is dependent on both the datum and the logical address.

公开(公告)号：US20210065834A1

公开(公告)日：2021-03-04

申请号：US17010400

申请日：2020-09-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Fabrice ROMAIN ,  Mathieu LISART

IPC: G11C29/44 ,  G11C29/42 ,  G11C29/14

Abstract: A method for detecting a writing error of a datum in memory includes: storing at least two parts of equal size of a binary word representative of said datum at the same address in at least two identical memory circuits, and comparing internal control signals of the two memory circuits to determine existence of the writing error.

公开(公告)号：US20220310192A1

公开(公告)日：2022-09-29

申请号：US17839168

申请日：2022-06-13

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Fabrice ROMAIN ,  Mathieu LISART

IPC: G11C29/44 ,  G11C29/14 ,  G11C29/42

Abstract: A method for detecting a reading error of a datum in memory. A binary word which is representative of the datum and an error correcting or detecting code is read by: reading a first part of the binary word stored at a first address in a first memory circuit; and reading a second part of the binary word stored at a second address in a second memory circuit. The first and second parts read from the first and second memory circuits, respectively, are concatenated to form a read binary word. The datum is then obtained by removing the error correcting or detecting code from the read binary word. A new error correcting or detecting code is calculated from the obtained datum and compared to the removed error correcting or detecting code to detect error in the obtained datum.

公开(公告)号：US20190087355A1

公开(公告)日：2019-03-21

申请号：US16130858

申请日：2018-09-13

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Fabrice ROMAIN

IPC: G06F12/14 ,  G06F11/00

CPC classification number: G06F12/1458 ,  G06F11/006 ,  G06F12/1408 ,  G06F2201/805 ,  G06F2212/1052 ,  G06F2221/2141

Abstract: The present disclosure concerns a memory access control system comprising: a processing device capable of operating in a plurality of operating modes, and of accessing a memory using a plurality of address aliases; and a verification circuit configured: to receive, in relation with a first read operation of a first memory location in the memory, an indication of a first of said plurality of address aliases associated with the first read operation; to verify that a current operating mode of the processing device permits the processing device to access the memory using the first address alias; to receive, during the first read operation, a first marker stored at the first memory location; and to verify, based on the first marker and on the first address alias, that the processing device is permitted to access the first memory location.