公开(公告)号：US20240014819A1

公开(公告)日：2024-01-11

申请号：US17861067

申请日：2022-07-08

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Mark WALLIS ,  Jean-Francois LINK ,  Joran PANTEL

IPC: H03K19/17724 ,  H03K19/17736 ,  H03K19/173 ,  H03K19/20

CPC classification number: H03K19/17724 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/1737 ,  H03K19/20

Abstract: An integrated circuit includes a programmable logic block. The programmable logic block includes a programmable logic array (PLA) and a field programmable gate array (FPGA). The PLA includes logic cells having a first architecture. The FPGA includes logic cells having a second architecture more complex than the first architecture. The programmable logic block includes an interface coupled to the PLA and the FPGA. An integrated circuit may also include circuitry for selecting one of plurality of clock signals for logic cells of a PLA.

公开(公告)号：US20230353154A1

公开(公告)日：2023-11-02

申请号：US17733934

申请日：2022-04-29

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Jean-Francois LINK ,  Mark WALLIS ,  Joran PANTEL

IPC: H03K19/17736 ,  H03K19/173

CPC classification number: H03K19/17744 ,  H03K19/1737 ,  H03K19/1774

Abstract: A system on chip includes a programmable logic array. The system on chip also includes a signal conditioner coupled to a data input of the programmable logic array and configured to condition a data signal prior to processing the data signal with the programmable logic array. The signal conditioner can selectively condition the signal by one or both of synchronizing the data signal with a clock signal of the programmable logic array and generating a pulse from the data signal with an edge detector.

公开(公告)号：US20240176979A1

公开(公告)日：2024-05-30

申请号：US18432679

申请日：2024-02-05

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Jose MANGIONE ,  Andrei TUDOSE ,  Pierre Yves BAUDRION ,  Joran PANTEL

IPC: G06K19/077 ,  G06K19/07 ,  H01Q7/00 ,  H04B5/24 ,  H04B5/77

CPC classification number: G06K19/07798 ,  G06K19/0722 ,  H01Q7/00 ,  H04B5/24 ,  H04B5/77

Abstract: A method is presented for monitoring a tampering state of closed container wherein a first electrically conductive wire extends across a slot between two portions of the closed container. The method includes applying a voltage across the first electrically conductive wire, sensing a voltage at one end of the first electrically conductive wire, and generating a signal indicating the tampering state of the closed container in response to the sensed voltage. The sensed voltage has a first voltage value if the first electrically conductive wire has been severed by tampering, and this tampered state is then reported using near field communication. The near field communication is blocked if it is sensed that the severed first electrically conductive wire has been repaired.

公开(公告)号：US20230387917A1

公开(公告)日：2023-11-30

申请号：US17827515

申请日：2022-05-27

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Jean-Francois LINK ,  Mark WALLIS ,  Joran PANTEL

IPC: H03K19/17724 ,  H03K19/173 ,  H03K19/17704 ,  H03K19/096 ,  H03K3/0233

CPC classification number: H03K19/17724 ,  H03K19/1737 ,  H03K19/17708 ,  H03K19/096 ,  H03K3/0233

Abstract: An integrated circuit includes a programmable logic array. The programmable logic array incudes a plurality of logic elements arranged in rows and columns. Each logic element includes a direct output and a synchronized output. The direct output of each logic element is coupled to all other logic elements of higher rank, but is not coupled to logic elements of lower rank.

公开(公告)号：US20240267050A1

公开(公告)日：2024-08-08

申请号：US18641199

申请日：2024-04-19

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Jean-Francois LINK ,  Mark WALLIS ,  Joran PANTEL

IPC: H03K19/17736 ,  H03K19/173

CPC classification number: H03K19/17744 ,  H03K19/1737 ,  H03K19/1774

Abstract: A system on chip includes a programmable logic array. The system on chip also includes a signal conditioner coupled to a data input of the programmable logic array and configured to condition a data signal prior to processing the data signal with the programmable logic array. The signal conditioner can selectively condition the signal by one or both of synchronizing the data signal with a clock signal of the programmable logic array and generating a pulse from the data signal with an edge detector.

公开(公告)号：US20240178842A1

公开(公告)日：2024-05-30

申请号：US18435913

申请日：2024-02-07

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Mark WALLIS ,  Jean-Francois LINK ,  Joran PANTEL

IPC: H03K19/17724 ,  H03K19/173 ,  H03K19/17736 ,  H03K19/20

CPC classification number: H03K19/17724 ,  H03K19/1737 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/20

Abstract: An integrated circuit includes a programmable logic block. The programmable logic block includes a programmable logic array (PLA) and a field programmable gate array (FPGA). The PLA includes logic cells having a first architecture. The FPGA includes logic cells having a second architecture more complex than the first architecture. The programmable logic block includes an interface coupled to the PLA and the FPGA. An integrated circuit may also include circuitry for selecting one of plurality of clock signals for logic cells of a PLA.

公开(公告)号：US20210397920A1

公开(公告)日：2021-12-23

申请号：US17292149

申请日：2019-10-23

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Jose MANGIONE ,  Andrei TUDOSE ,  Pierre Yves BAUDRION ,  Joran PANTEL

IPC: G06K19/077 ,  H01Q7/00 ,  G06K19/07 ,  H04B5/00

Abstract: A closed container includes a detection device for detecting opening of or an attempt to open the container. The detection device includes a contactless passive transponder that is configured to communicate with a reader via an antenna using a carrier signal. An integrated circuit of the transponder includes two input terminals connected to the antenna and two output terminals linked by a first electrically conductive wire having a severable part which is severed in the event of an opening of or an attempted opening of the container. A shorting circuit is configured to short-circuit a first output terminal with a first input terminal in the event of a conductive repair of the severed part which forms an electrical connection between the two output terminals.