公开(公告)号：US20240136350A1

公开(公告)日：2024-04-25

申请号：US18485190

申请日：2023-10-11

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Loic BOURGUINE ,  Lionel ESTEVE

IPC: H01L27/02 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L27/0285 ,  H01L27/0288 ,  H01L28/24 ,  H01L29/2003 ,  H01L29/7787

Abstract: The present disclosure concerns overtemperature protection circuit formed inside and on top of a monolithic semiconductor substrate having a surface covered with a gallium nitride layer, comprising:



a first resistor having a first positive temperature coefficient and being arranged in said gallium nitride layer; and
a second resistor having a second temperature coefficient different from the first coefficient.

公开(公告)号：US20240136351A1

公开(公告)日：2024-04-25

申请号：US18485201

申请日：2023-10-11

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Loic BOURGUINE ,  Lionel ESTEVE

IPC: H01L27/06 ,  H01L27/088 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L27/0605 ,  H01L27/0629 ,  H01L27/0886 ,  H01L29/2003 ,  H01L29/7783 ,  H01L29/7787

Abstract: The present disclosure concerns a voltage regulation circuit formed inside and on top of a monolithic semiconductor substrate having a surface covered with a gallium nitride layer, comprising: between a first terminal and a second terminal, a first resistor and a first d-mode type HEMT transistor; and between the first terminal and the third terminal, a second d-mode type HEMT transistor; wherein the midpoint between the first resistor and the first transistor is coupled to the gates of the first and second transistors.

公开(公告)号：US20240136433A1

公开(公告)日：2024-04-25

申请号：US18485184

申请日：2023-10-11

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Loic BOURGUINE ,  Lionel ESTEVE ,  Antoine PAVLIN

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/417

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/41758 ,  H02H3/08

Abstract: The present disclosure concerns an electronic device formed inside and on top of a monolithic semiconductor substrate having a surface covered with a gallium nitride layer, comprising at least one e-mode type HEMT power transistor adapted to receiving a maximum voltage of 650 V between its drain and its source, and an analog circuit for controlling said power transistor.

公开(公告)号：US20240136424A1

公开(公告)日：2024-04-25

申请号：US18485194

申请日：2023-10-11

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Loic BOURGUINE

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/7788

Abstract: The present disclosure concerns a driver of a first e-mode type HEMT power transistor adapted to receiving a maximum voltage of 650 V between its drain and its source, the circuit being formed inside and on top of a monolithic semiconductor substrate having a surface covered with a gallium nitride layer, and comprising at least a second e-mode type transistor adapted to directly transmitting a control voltage to the gate of the first transistor and having an area greater than 5 mm2.