公开(公告)号：US20240322031A1

公开(公告)日：2024-09-26

申请号：US18578739

申请日：2022-07-12

申请人： IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY)

发明人： Jea Gun PARK ,  Jin Pyo HONG ,  Min Won KIM ,  Byoung Seok LEE ,  Ji Hun KIM

IPC分类号： H01L29/778 ,  H01L21/762 ,  H01L29/08 ,  H01L29/16

CPC分类号： H01L29/7788 ,  H01L21/76243 ,  H01L29/0847 ,  H01L29/16

摘要： The present invention relates to a transistor based on a compact drain and hetero-material structure. The transistor according to one embodiment includes substrates including a buried oxide (BOX) layer and active layers formed on the buried oxide layer; an insulating layer formed on the substrates; and electrode layers formed on the insulating layer and including a drain electrode, a gate electrode, and a source electrode. The active layers include a first semiconductor layer corresponding to a drain region, a second semiconductor layer corresponding to a channel region, and a third semiconductor layer corresponding to a source region. The first semiconductor layer is formed to be thinner than the second semiconductor layer, and the third semiconductor layer is formed of a material having a band gap lower than that of the second semiconductor layer.

公开(公告)号：US12094964B2

公开(公告)日：2024-09-17

申请号：US18332119

申请日：2023-06-09

申请人： NaMLab gGmbH ,  Technische Universität Dresden

发明人： Stefan Schmult ,  Andre Wachowiak ,  Alexander Ruf

IPC分类号： H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/22 ,  H01L29/225

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/22 ,  H01L29/225 ,  H01L29/7788

摘要： An electronic circuit having a semiconductor device is provided that includes a heterostructure, the heterostructure including a first layer of a compound semiconductor to which a second layer of a compound semiconductor adjoins in order to form a channel for a 2-dimensional electron gas (2DEG), wherein the 2-dimensional electron gas is not present. In aspects, an electronic circuit having a semiconductor device is provided that includes a III-V heterostructure, the III-V heterostructure including a first layer including GaN to which a second layer adjoins in order to form a channel for a 2-dimensional electron gas (2DEG), and having a purity such that the 2-dimensional electron gas is not present. It is therefore advantageous for the present electronic circuit to be enclosed such that, in operation, no light of wavelengths of less than 400 nm may reach the III-V heterostructure and free charge carriers may be generated by these wavelengths.

公开(公告)号：US12087762B2

公开(公告)日：2024-09-10

申请号：US17259505

申请日：2019-07-11

申请人： PANASONIC CORPORATION

发明人： Daisuke Shibata ,  Satoshi Tamura ,  Masahiro Ogawa

IPC分类号： H01L29/778 ,  H01L21/265 ,  H01L21/266 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8252 ,  H01L27/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/872

CPC分类号： H01L27/0605 ,  H01L21/26546 ,  H01L21/266 ,  H01L21/30621 ,  H01L21/308 ,  H01L21/8252 ,  H01L27/0629 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66212 ,  H01L29/66462 ,  H01L29/7788 ,  H01L29/872

摘要： Nitride semiconductor device includes: a substrate; a first nitride semiconductor layer of a first conductivity above the substrate; a second nitride semiconductor layer of a second conductivity different from the first conductivity, above the first nitride semiconductor layer; a first opening penetrating through the second nitride semiconductor layer; an electron transport layer and an electron supply layer disposed along inner surfaces of the first opening, in stated sequence from the substrate-side; a gate electrode above the electron supply layer, covering the first opening; a source electrode connected to the electron supply layer and the electron transport layer, at a position separated from the gate electrode; and a drain electrode on a surface of the substrate opposite to a surface on which the first nitride semiconductor layer is disposed. At least part of the second nitride semiconductor layer is fixed to a potential different from a potential of the source electrode.

公开(公告)号：US20240222490A1

公开(公告)日：2024-07-04

申请号：US18400480

申请日：2023-12-29

申请人： GUANGDONG ZHINENG TECHNOLOGIES, CO. LTD.

发明人： Zilan LI ,  Lezhi WANG

IPC分类号： H01L29/778 ,  H01L29/417 ,  H01L29/66

CPC分类号： H01L29/7788 ,  H01L29/41775 ,  H01L29/66462

摘要： The present invention relates to a semiconductor device, including: a first channel layer; a second channel layer; a first barrier layer, where a vertical first two-dimensional carrier gas is included at the position in the first channel layer close to an interface between the first channel layer and the first barrier layer; a second barrier layer, where a vertical second two-dimensional carrier gas is included at the position in the second channel layer close to an interface between the second channel layer and the second barrier layer, and the first channel layer and the second channel layer are located between the first barrier layer and the second barrier layer; a source electrode electrically connected to the first two-dimensional carrier gas and the second two-dimensional carrier gas; a drain electrode electrically connected to the first two-dimensional carrier gas and the second two-dimensional carrier gas; and a gate electrode located between the source electrode and the drain electrode, where the first channel layer and the second channel layer are doped such that the first two-dimensional carrier gas between the first channel layer and the gate electrode and the second two-dimensional carrier gas between the second channel layer and the gate electrode are depleted. The present application further relates to a manufacturing method for a semiconductor device.

公开(公告)号：US11978792B2

公开(公告)日：2024-05-07

申请号：US14761010

申请日：2014-01-15

申请人： VISIC TECHNOLOGIES LTD.

发明人： Gregory Bunin ,  Tamara Baksht

IPC分类号： H01L29/778 ,  H01L23/535 ,  H01L29/417 ,  H01L29/20 ,  H01L29/423

CPC分类号： H01L29/7788 ,  H01L23/535 ,  H01L29/417 ,  H01L29/7783 ,  H01L29/7786 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/4236 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

摘要： A field effect transistor (FET) includes a plurality of substantially parallel conductive channels and at least one electrically conducting plug to travers and form an ohmic connection with at least two of the plurality of conductive channels.

公开(公告)号：US11908905B2

公开(公告)日：2024-02-20

申请号：US17867012

申请日：2022-07-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yao-Chung Chang ,  Chun Lin Tsai ,  Ru-Yi Su ,  Wei Wang ,  Wei-Chen Yang

IPC分类号： H01L29/417 ,  H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/868

CPC分类号： H01L29/417 ,  H01L29/41741 ,  H01L29/6609 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7788 ,  H01L29/868

摘要： Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure, the method includes forming a buffer layer over a substrate. An active layer is formed on the buffer layer. A top electrode is formed on the active layer. An etch process is performed on the buffer layer and the substrate to define a plurality of pillar structures. The plurality of pillar structures include a first pillar structure laterally offset from a second pillar structure. At least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode.

公开(公告)号：US20240030356A1

公开(公告)日：2024-01-25

申请号：US18247753

申请日：2021-10-05

申请人： The Penn State Research Foundation

发明人： Sang-Woo Han ,  Jianan Song ,  Rongming Chu ,  Mansura Sadek

IPC分类号： H01L29/872 ,  H01L29/06 ,  H01L29/66 ,  H01L29/778 ,  H01L29/78

CPC分类号： H01L29/872 ,  H01L29/0634 ,  H01L29/66212 ,  H01L29/7788 ,  H01L29/7806

摘要： Embodiments relate a super-heterojunction structure. A n-type modulation doping with barrier layer induces a two-dimensional electron gas (2DEG) channel and allows for vertically stacked channels without risk of reaching critical thickness limited by the strain in epitaxy. The n-type modulation doped layer is adjacent the at least one p-type layer to generate a charge balanced super-heterojunction region. A p-type ohmic contact ensures that the processes of depleting and accumulating of electrons and holes in the structure are fast enough for practical switching operation.

公开(公告)号：US20230361126A1

公开(公告)日：2023-11-09

申请号：US18137093

申请日：2023-04-20

申请人： Nexgen Power Systems, Inc.

发明人： Andrew P. Edwards ,  Andrew J. Walker ,  Clifford Drowley ,  Subhash Srinivas Pidaparthi

IPC分类号： H01L27/095 ,  H01L29/778 ,  H01L29/20

CPC分类号： H01L27/095 ,  H01L29/7788 ,  H01L29/2003

摘要： A vertical fin-based field effect transistor (FinFET) device includes an array of FinFETs comprising a plurality of rows and columns of fins, each of the fins having a fin length and a fin width measured laterally with respect to the fin length and including a first fin tip disposed at a first end of the fin; a second fin tip disposed at a second end of the fin opposing the first end; a bridging structure connecting the first fin tip to an adjacent fin; a central region disposed between the first fin tip and the second fin tip and characterized by an electrical conductivity; and a source contact electrically coupled to the central region. The FinFET device also includes a gate region surrounding the fins.

公开(公告)号：US20230352575A1

公开(公告)日：2023-11-02

申请号：US17999605

申请日：2021-05-27

申请人： Epinovatech AB

发明人： Martin Andreas Olsson

IPC分类号： H01L29/778 ,  H01L29/06 ,  H01L29/66

CPC分类号： H01L29/7788 ,  H01L29/0676 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/0646 ,  H01L29/2003

摘要： There is provided a vertical high-electron-mobility transistor, HEMT (100), comprising: a drain contact (410), a nanowire layer (500) arranged on the drain contact (410) and comprising at least one vertical nanowire (510) and a supporting material (520) laterally enclosing the at least one vertical nanowire (510), a heterostructure (600) arranged on the nanowire layer and comprising an AIGaN-layer (610) and a GaN-layer (620) together forming a heterojunction, at least one source contact (420a, 420b) in contact with the heterostructure (600), and a gate contact (430) in contact with the heterostructure (600), arranged above the at least one vertical nanowire (510), wherein the at least one vertical nanowire (510) is forming an electron transport channel between the drain contact and the heterostructure. There is also provided a method for producing a vertical HEMT (100).

公开(公告)号：US20180315844A1

公开(公告)日：2018-11-01

申请号：US15771083

申请日：2016-10-28

申请人： The Hong Kong University of Science and Technology

发明人： Jing CHEN ,  Jin WEI

IPC分类号： H01L29/778 ,  H01L29/66 ,  H01L29/267 ,  H01L29/20 ,  H01L29/16 ,  H01L29/423 ,  H01L29/06

CPC分类号： H01L29/267 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/085 ,  H01L29/0623 ,  H01L29/0646 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7788 ,  H01L29/808

摘要： Techniques are provided for forming a semiconductor device. In an aspect, a semiconductor device is provided that includes a silicon carbide (SiC) structure and a III-nitride structure. The SiC structure includes a drain electrode, a substrate layer that is formed on the drain electrode and includes SiC, and a drift layer formed on the substrate layer. The drift layer includes p-well regions that allow current to flow through a region between the p-well regions. The III-nitride structure includes a set of III-nitride semiconductor layers formed on the SiC structure, a passivation layer formed on the set of III-nitride semiconductor layers, a source electrode electrically coupled to the p-well regions, and gate electrodes electrically isolated from the set of III-nitride semiconductor layers. In an aspect, the SiC structure includes a transition layer that includes connecting regions. In another aspect, the III-nitride structures includes connection electrodes electrically coupled to the connecting regions.