公开(公告)号：US20240324196A1

公开(公告)日：2024-09-26

申请号：US18735967

申请日：2024-06-06

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Franck Melul ,  Abderrezak Marzaki ,  Madjid Akbal

IPC: H10B41/35 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788 ,  H10B41/10

CPC classification number: H10B41/35 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34 ,  H01L29/66825 ,  H01L29/7884 ,  H01L29/40114 ,  H01L29/7883 ,  H10B41/10

Abstract: In an embodiment a memory cell includes a first doped well of a first conductivity type embedded in a second doped well of a second conductivity type, the second conductivity type being opposite to the first conductivity type, a third doped well of the second conductivity type embedded in a fourth doped well of the first conductivity type, a first wall in contact with the second and fourth doped wells, the first wall including a conductive or semiconductor core and an insulating liner, the insulating liner extending between the conductive or semiconductor core and the second and fourth doped wells, and a stack of layers comprising a first insulating layer, a first semiconductor layer, a second insulating layer and a second semiconductor layer, the first insulating layer being in contact with the second and fourth doped wells.

公开(公告)号：US12035522B2

公开(公告)日：2024-07-09

申请号：US17700323

申请日：2022-03-21

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Franck Melul ,  Abderrezak Marzaki ,  Madjid Akbal

IPC: H10B41/35 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788 ,  H10B41/10

CPC classification number: H10B41/35 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34 ,  H01L29/66825 ,  H01L29/7884 ,  H01L29/40114 ,  H01L29/7883 ,  H10B41/10

Abstract: In an embodiment a memory cell includes a first doped well of a first conductivity type in contact with a second doped well of a second conductivity type, the second conductivity type being opposite to the first conductivity type, a third doped well of the second conductivity type in contact with a fourth doped well of the first conductivity type, a first wall in contact with the second and fourth wells, the first wall including a conductive or semiconductor core and an insulating sheath, a stack of layers including a first insulating layer, a first semiconductor layer, a second insulating layer and a second semiconductor layer at least partially covering the second and fourth wells and a third semiconductor layer located below the second and fourth wells and the first wall.

公开(公告)号：US20220328509A1

公开(公告)日：2022-10-13

申请号：US17700323

申请日：2022-03-21

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Franck Melul ,  Abderrezak Marzaki ,  Madjid Akbal

IPC: H01L27/11524 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34 ,  H01L29/788 ,  H01L29/66

Abstract: In an embodiment a memory cell includes a first doped well of a first conductivity type in contact with a second doped well of a second conductivity type, the second conductivity type being opposite to the first conductivity type, a third doped well of the second conductivity type in contact with a fourth doped well of the first conductivity type, a first wall in contact with the second and fourth wells, the first wall including a conductive or semiconductor core and an insulating sheath, a stack of layers including a first insulating layer, a first semiconductor layer, a second insulating layer and a second semiconductor layer at least partially covering the second and fourth wells and a third semiconductor layer located below the second and fourth wells and the first wall.