公开(公告)号：US20200081062A1

公开(公告)日：2020-03-12

申请号：US16128645

申请日：2018-09-12

Applicant: STMicroelectronics Asia Pacific Pte Ltd

Inventor： Beng-Heng GOH

IPC: G01R31/3177 ,  H03K19/20 ,  H03K5/133 ,  G06F1/10

Abstract: A glitch detector includes an input flip-flop clocked by a clock signal and having a non-inverting data output, an inverting data output, and a data input receiving input from the inverting data output, the input flip-flop generating a divided version of the clock signal at the non-inverting data output. A configurable delay chain receives the divided version of the clock signal and generates a delayed version of the divided version of the clock signal as a delay output. An intermediate flip-flop clocked by the clock signal has a data input receiving the delay output, the intermediate flip-flop generating an intermediate output as a function of the delay output. A logic circuit receives the divided version of the clock signal and the intermediate output, and generates a glitch detect signal by performing a logical operation on the divided version of the clock signal and the intermediate output.

公开(公告)号：US20190173458A1

公开(公告)日：2019-06-06

申请号：US16273317

申请日：2019-02-12

Applicant: STMicroelectronics Asia Pacific Pte Ltd

Inventor： Beng-Heng GOH ,  Yi Ren CHIN

IPC: H03K5/151 ,  G11C7/22 ,  G11C19/28 ,  H03L7/00

CPC classification number: H03K5/1515 ,  G11C7/22 ,  G11C7/222 ,  G11C19/28 ,  G11C19/287 ,  H03L7/00

Abstract: An electronic device includes clock generation circuitry. The clock generation circuitry includes a first flip flop receiving as input a device clock and being triggered by an input clock and a second flip flop receiving, as input, output from the first flip flop and being triggered by the input clock. A first inverter receives output from the first flip flop as input and a second inverter receives output from the second flip flop as input. A first AND gate receives, as input, output from the second flip flop and the first inverter, and generates a first clock as output. A second AND gate receives, as input, output from the first flip flop and the second inverter, and generates a second clock as output.