公开(公告)号：US10333397B2

公开(公告)日：2019-06-25

申请号：US15652748

申请日：2017-07-18

Applicant: STMicroelectronics International N.V.

Inventor： Vikas Rana ,  Abhishek Mittal

IPC: H02M3/07

Abstract: A charge pump includes boosting circuits cascade coupled between first and second nodes, wherein each boosting circuit is operable in both a positive voltage boosting mode to positively boost voltage and a negative voltage boosting mode to negatively boost voltage. A first switching circuit selectively applies a first voltage to one of the cascaded boosting circuits in response to a first logic state of a periodic enable signal, with the cascaded boosting circuits operating in the positive voltage boosting mode to produce a high positive voltage at the second node. A second switching circuit selectively applies a second voltage to another of the cascaded boosting circuits in response to a second logic state of the periodic enable signal, with the cascaded boosting circuits operating in the negative voltage boosting mode to produce a high negative voltage at the first node. Simultaneous output of the positive and negative voltages is made.

公开(公告)号：US11342031B2

公开(公告)日：2022-05-24

申请号：US17006510

申请日：2020-08-28

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Marco Pasotti ,  Dario Livornesi ,  Roberto Bregoli ,  Vikas Rana ,  Abhishek Mittal

IPC: G11C13/00 ,  G11C7/02 ,  G11C16/26 ,  G11C7/06 ,  G11C7/14 ,  G11C16/34 ,  G11C16/08 ,  G06F12/00

Abstract: An integrated circuit includes a memory array and a read voltage regulator that generates read voltages from the memory array. The read voltage regulator includes a replica memory cell and the replica bitline current path. The replica memory cell is a replica of memory cells of the memory array. The replica bitline current path is a replica of current paths associated with deadlines of the memory array. The read voltage regulator generates a read voltage based on the current passed through the replica bitline current path. This read voltage is then supplied to the wordlines of the memory array during a read operation.

公开(公告)号：US20190028026A1

公开(公告)日：2019-01-24

申请号：US15652748

申请日：2017-07-18

Applicant: STMicroelectronics International N.V.

Inventor： Vikas Rana ,  Abhishek Mittal

IPC: H02M3/07

CPC classification number: H02M3/073 ,  H02M2003/071

Abstract: A charge pump includes boosting circuits cascade coupled between first and second nodes, wherein each boosting circuit is operable in both a positive voltage boosting mode to positively boost voltage and a negative voltage boosting mode to negatively boost voltage. A first switching circuit selectively applies a first voltage to one of the cascaded boosting circuits in response to a first logic state of a periodic enable signal, with the cascaded boosting circuits operating in the positive voltage boosting mode to produce a high positive voltage at the second node. A second switching circuit selectively applies a second voltage to another of the cascaded boosting circuits in response to a second logic state of the periodic enable signal, with the cascaded boosting circuits operating in the negative voltage boosting mode to produce a high negative voltage at the first node. Simultaneous output of the positive and negative voltages is made.