公开(公告)号：US20250070785A1

公开(公告)日：2025-02-27

申请号：US18236038

申请日：2023-08-21

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan SRINIVASAN ,  Ajay Kumar DIMRI

IPC: H03L7/08 ,  G01R31/28 ,  H03K3/037 ,  H03K19/20

Abstract: A test-circuit includes a PLL-divider outputting first and third clock-signals as PLL clock-signals during functional mode and a capture-phase of transition and stuck-at-modes, and outputting a second clock-signal based upon an external clock-signal as an ATE clock-signal during a shift-phase of the transition and stuck-at-mode. An OCC passes the clock-signals in functional mode, transition capture mode, and stuck-at capture mode through sub-paths within first paths within first and second clock selection circuits so the first and third clock-signals are passed through less than the entire first paths, the sub-paths being first and second functional clock paths. In shift phase of transition and stuck-at-modes, the OCC passes the second clock-signal through sub-paths within second paths within the first and second clock selection circuits during the shift-phase so the second clock-signal is passed through less than the entire second paths, and through the first and second functional clock paths during the shift-phase.