公开(公告)号：US20250038670A1

公开(公告)日：2025-01-30

申请号：US18225955

申请日：2023-07-25

Applicant: STMicroelectronics International N.V.

Inventor： Stefano PERROTTA ,  Salvatore Giuseppe PRIVITERA ,  Francesco PULVIRENTI

IPC: H02M3/335 ,  H02M1/00

Abstract: A DC-DC converter includes a primary-side control-circuit having an oscillator driving a transformer in response to assertion of a PWM-signal to transmit power from the primary to the secondary and ceasing in response to deassertion of the PWM-signal, and a receiver demodulator circuit receiving/demodulating a feedback signal sent from the secondary to the primary by comparing an instantaneous value of an envelope indicative of voltages at the primary-coil to an average-value of the envelope to produce a reset-signal. A PWM circuit asserts the PWM-signal in response to a set-signal and deasserts the PWM-signal in response to assertion of the reset-signal. A secondary-side control-circuit rectifies the received power, asserts an intermediate feedback-signal if feedback indicative of the output voltage is greater than a reference-voltage, and connects a capacitance between the secondary and ground in response to assertion of the intermediate feedback-signal to modulate and send the feedback to the primary.

公开(公告)号：US20240322814A1

公开(公告)日：2024-09-26

申请号：US18604239

申请日：2024-03-13

Applicant: STMicroelectronics International N.V.

Inventor： Francesco PULVIRENTI ,  Salvatore Giuseppe PRIVITERA ,  Cesare BIMBI

IPC: H03K17/16 ,  H03K17/10 ,  H03K17/687

CPC classification number: H03K17/162 ,  H03K17/102 ,  H03K17/6872

Abstract: A buffer circuit for driving a GaN power switch includes an input node to receive an input signal and an output node to produce a gate signal for the GaN power switch. The buffer includes a push-pull stage that includes a first transistor coupled between a supply voltage node and the output node, a second transistor coupled between the supply voltage node and the output node, a third transistor coupled between the output node and a reference voltage node, and a fourth transistor coupled between the output node and the reference voltage node. The buffer includes a pre-buffer stage configured to receive the input signal and to produce respective driving signals for the first, second, third and fourth transistors to produce the gate signal at the output node in four consecutive phases.