公开(公告)号：US20240274572A1

公开(公告)日：2024-08-15

申请号：US18415006

申请日：2024-01-17

Applicant: STMicroelectronics International N.V.

Inventor： Jefferson Sismundo TALLEDO

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/495

CPC classification number: H01L24/84 ,  H01L21/4842 ,  H01L21/561 ,  H01L23/49582 ,  H01L24/40 ,  H01L24/97 ,  H01L21/565 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/32245 ,  H01L2224/40245 ,  H01L2224/73263 ,  H01L2224/84947 ,  H01L2224/92246 ,  H01L2224/97 ,  H01L2924/13091

Abstract: An etched leadframe includes separated frame portions, where each frame portion includes an intermediate region interposed between lead and die pad regions. An integrated circuit die is mounted to each die pad region. A clip is mounted to each integrated circuit die, wherein the clip includes a lead mounting portion mounted to the lead region of an adjacent frame portion and a bridge portion extending over the intermediate region of the adjacent frame portion and mounted to the die pad region of the adjacent frame portion. A first cut made through the frame portion of each etched leadframe at the intermediate region separates the lead and die pad regions without severing the bridge portion of each clip. A conductive layer is plated on full sidewalls of the lead and die pad regions exposed by the first cut. A second cut is then made through the bridge portion of each clip.