公开(公告)号：US20240256154A1

公开(公告)日：2024-08-01

申请号：US18420263

申请日：2024-01-23

Applicant: STMicroelectronics International N.V.

Inventor： Michael GIOVANNINI

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0634 ,  G06F3/0673

Abstract: A system includes a memory formed by memory units accessible in write mode and in read mode. Each memory unit includes an array of memory cells and a peripheral circuit of access to the memory cells. Each memory unit is configurable in a first operating mode and a second operating mode. The array of memory cells are set in the first operating mode and the second operating modes to retain data until a subsequent powering off of the memory unit. The peripheral circuit is powered in the first operating mode and is not powered in the second operating mode. A controller configures any memory unit of the memory having undergone no write or read access for a determined time period to be in the second operating mode.

公开(公告)号：US20250077649A1

公开(公告)日：2025-03-06

申请号：US18810040

申请日：2024-08-20

Applicant: STMicroelectronics International N.V.

Inventor： Michael GIOVANNINI

IPC: G06F21/54 ,  G06F21/55 ,  G06F21/85

Abstract: Provided is a module for monitoring instructions of a microcontroller. The module is adapted to receive instructions that are received at an input terminal of the microcontroller or that are being processed by a code pointer of the microcontroller. The module verifies the instructions received on the input terminal of the microcontroller or that are being processed by the code pointer of the microcontroller.