公开(公告)号：US12212318B2

公开(公告)日：2025-01-28

申请号：US18098421

申请日：2023-01-18

Applicant: STMicroelectronics International N.V.

Inventor： Sandeep Kaushik ,  Paras Garg

IPC: H03K19/0185 ,  H03K17/687 ,  H03K19/017

Abstract: A Low Voltage Differential Signaling (LVDS) transmitter includes driver circuit with a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, and a second resistor. The first transistor is coupled between a first node and first output. The second transistor is coupled between the first node and a second output. The third transistor is coupled between the first output and a second node. The fourth transistor is coupled between the second output and the second node. The first resistor is coupled between the first output and a common mode node. The second resistor is coupled between the second output and the common mode node. A pre-driver circuit generates gate control signals controlling the first, second, third, and fourth transistors in response to a data signal. A controlled timing delay is applied to the timing of logic state transistors for the control signals.

公开(公告)号：US11223354B2

公开(公告)日：2022-01-11

申请号：US16999813

申请日：2020-08-21

Applicant: STMicroelectronics International N.V.

Inventor： Paras Garg ,  Ankit Agrawal ,  Sandeep Kaushik

IPC: H03K19/0185 ,  H03K17/687 ,  H03K5/24

Abstract: Low-voltage differential signaling (LVDS) receiver circuits, electronic devices, and methods are provided. A LVDS receiver includes an input differential pair of transistors that receive a differential input signal. The input differential pair includes a first NMOS transistor that receives a first input signal and a second NMOS transistor that receives a second input signal. A third NMOS transistor has source and drain terminals respectively coupled to source and drain terminals of the first NMOS transistor, and a fourth NMOS transistor has source and drain terminals respectively coupled to source and drain terminals of the second NMOS transistor. A first level shifter is coupled to a gate of the third NMOS transistor, and a second level shifter is coupled to a gate of the fourth NMOS transistor.