公开(公告)号：US11223354B2

公开(公告)日：2022-01-11

申请号：US16999813

申请日：2020-08-21

Applicant: STMicroelectronics International N.V.

Inventor： Paras Garg ,  Ankit Agrawal ,  Sandeep Kaushik

IPC: H03K19/0185 ,  H03K17/687 ,  H03K5/24

Abstract: Low-voltage differential signaling (LVDS) receiver circuits, electronic devices, and methods are provided. A LVDS receiver includes an input differential pair of transistors that receive a differential input signal. The input differential pair includes a first NMOS transistor that receives a first input signal and a second NMOS transistor that receives a second input signal. A third NMOS transistor has source and drain terminals respectively coupled to source and drain terminals of the first NMOS transistor, and a fourth NMOS transistor has source and drain terminals respectively coupled to source and drain terminals of the second NMOS transistor. A first level shifter is coupled to a gate of the third NMOS transistor, and a second level shifter is coupled to a gate of the fourth NMOS transistor.

公开(公告)号：US12212318B2

公开(公告)日：2025-01-28

申请号：US18098421

申请日：2023-01-18

Applicant: STMicroelectronics International N.V.

Inventor： Sandeep Kaushik ,  Paras Garg

IPC: H03K19/0185 ,  H03K17/687 ,  H03K19/017

Abstract: A Low Voltage Differential Signaling (LVDS) transmitter includes driver circuit with a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, and a second resistor. The first transistor is coupled between a first node and first output. The second transistor is coupled between the first node and a second output. The third transistor is coupled between the first output and a second node. The fourth transistor is coupled between the second output and the second node. The first resistor is coupled between the first output and a common mode node. The second resistor is coupled between the second output and the common mode node. A pre-driver circuit generates gate control signals controlling the first, second, third, and fourth transistors in response to a data signal. A controlled timing delay is applied to the timing of logic state transistors for the control signals.

公开(公告)号：US09473135B2

公开(公告)日：2016-10-18

申请号：US14500076

申请日：2014-09-29

Applicant: STMicroelectronics International N.V.

Inventor： Paras Garg ,  Rajesh Yadav ,  Saiyid Mohammad Irshad Rizvi ,  Ravinder Kumar

IPC: H03K3/00 ,  H03K17/687 ,  H03K19/0185

CPC classification number: H03K17/687 ,  H03K19/0185 ,  H03K2217/0018

Abstract: A drive circuit includes a first drive transistor coupled between a first supply node and an output pad of an integrated circuit and a second drive transistor coupled between a second supply node and the output pad. The first drive transistor and second drive transistors are controlled by a control signal. A body bias generator circuit is configured to apply a variable first body bias to the first transistor and a variable second body bias to the second transistor. The variable first and second body biases are generated as a function of the control signal and a voltage at the output pad.

Abstract translation: 驱动电路包括耦合在集成电路的第一电源节点和输出焊盘之间的第一驱动晶体管，以及耦合在第二电源节点和输出焊盘之间的第二驱动晶体管。 第一驱动晶体管和第二驱动晶体管由控制信号控制。 体偏置发生器电路被配置为将可变第一体偏置施加到第一晶体管，并将可变第二体偏置施加到第二晶体管。 可变的第一和第二体偏置作为控制信号和输出焊盘处的电压的函数产生。

公开(公告)号：US08981817B2

公开(公告)日：2015-03-17

申请号：US13926748

申请日：2013-06-25

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Vinod Kumar ,  Pradeep Kumar Badrathwal ,  Saiyid Mohammad Irshad Rizvi ,  Paras Garg ,  Kallol Chatterjee ,  Pierre Dautriche

IPC: H03K3/00

CPC classification number: H03K19/00384

Abstract: A circuit having a centralized PT compensation circuit to provide compensation signals to localized I/O blocks on the chip. Process variations and temperature variations tend to be approximately uniform across an integrated circuit chip. Thus, a single, centralized PT compensation circuit may be used instead of one PT compensation circuit per I/O section as with solutions of the past. Further, the PT compensation circuit may generate a digital code indicative of the effects of process and temperature. Further yet, each section of I/O block may have a local voltage compensation circuit to compensate the voltage variation of the I/O block. The voltage compensation circuit utilizes an independent reference voltage. The reference voltage is generated by the PT compensation circuit, which is placed centrally in the IC chip and hence any need to repeat the reference generation for each I/O block is eliminated.

Abstract translation: 具有集中PT补偿电路以向芯片上的局部I / O块提供补偿信号的电路。 整个集成电路芯片的工艺变化和温度变化趋向于大致均匀。 因此，与过去的解决方案一样，可以使用单个集中式PT补偿电路来代替每个I / O部分的一个PT补偿电路。 此外，PT补偿电路可以产生指示过程和温度的影响的数字代码。 此外，I / O块的每个部分可以具有用于补偿I / O块的电压变化的局部电压补偿电路。 电压补偿电路采用独立的参考电压。 参考电压由放置在IC芯片中央的PT补偿电路产生，因此不需要重复每个I / O块的参考生成。

公开(公告)号：US10530366B1

公开(公告)日：2020-01-07

申请号：US16503960

申请日：2019-07-05

Applicant: STMicroelectronics International N.V.

Inventor： Atul Dwivedi ,  Paras Garg ,  Kallol Chatterjee

IPC: H03K19/007 ,  H03K19/0185 ,  G01R31/317

Abstract: A low-voltage-differential-signaling (LVDS) fault detector includes first and second LVDS lines, and a window comparator provides a first output indicating whether a difference between voltages at the first and second LVDS lines is greater than a threshold voltage, and a second output indicating whether a difference between the voltages at the second and first LVDS lines is greater than the threshold voltage. A charge circuit charges a capacitive node when either the first or second output is at a logic low, and discharges the capacitive node when neither the first nor second output is at a logic low. A Schmitt trigger generates a fault flag if charge on the capacitive node falls to a threshold.

公开(公告)号：US20160094217A1

公开(公告)日：2016-03-31

申请号：US14500076

申请日：2014-09-29

Applicant: STMicroelectronics International N.V.

Inventor： Paras Garg ,  Rajesh Yadav ,  Saiyid Mohammad Irshad Rizvi ,  Ravinder Kumar

IPC: H03K17/687

CPC classification number: H03K17/687 ,  H03K19/0185 ,  H03K2217/0018

Abstract: A drive circuit includes a first drive transistor coupled between a first supply node and an output pad of an integrated circuit and a second drive transistor coupled between a second supply node and the output pad. The first drive transistor and second drive transistors are controlled by a control signal. A body bias generator circuit is configured to apply a variable first body bias to the first transistor and a variable second body bias to the second transistor. The variable first and second body biases are generated as a function of the control signal and a voltage at the output pad.

Abstract translation: 驱动电路包括耦合在集成电路的第一电源节点和输出焊盘之间的第一驱动晶体管，以及耦合在第二电源节点和输出焊盘之间的第二驱动晶体管。 第一驱动晶体管和第二驱动晶体管由控制信号控制。 体偏置发生器电路被配置为将可变第一体偏置施加到第一晶体管，并将可变第二体偏置施加到第二晶体管。 可变的第一和第二体偏置作为控制信号和输出焊盘处的电压的函数产生。