Charge pump regulation circuit to increase program and erase efficiency in nonvolatile memory

    公开(公告)号:US11070128B2

    公开(公告)日:2021-07-20

    申请号:US16715209

    申请日:2019-12-16

    IPC分类号: H02M3/07 G11C16/30 G11C5/14

    摘要: A charge pump circuit generates a charge pump output signal at a first node and is enabled by a charge pump control signal. A diode has first and second terminals coupled to first and second nodes. A comparator has an inverting input coupled to the second node and a non-inverting input coupled to a third node, and causes generation of the charge pump control signal. A first current mirror produces a first current at the second node, and a second current mirror produces a second current (equal in magnitude to the first current) at the third node. The first terminal and second terminals may be a cathode and an anode. The first current mirror may be a current sink sinking a first current from the second node. The second current mirror may be current source sourcing a second current (equal in magnitude to the first current) to the third node.

    Charge pump regulation circuit to increase program and erase efficiency in nonvolatile memory

    公开(公告)号:US11258358B2

    公开(公告)日:2022-02-22

    申请号:US16742248

    申请日:2020-01-14

    IPC分类号: H02M3/07

    摘要: A charge pump circuit generates a charge pump output signal at a first node and is enabled by a control signal. A diode has an anode coupled to the first node and a cathode coupled to a second node. A current mirror arrangement sources a first current to the second node and sinks a second current from a third node. A comparator causes the control signal to direct the charge pump circuit to generate the charge pump output signal as having a voltage that ramps upwardly in magnitude (but negative in sign) if the voltage at the second node is greater than the voltage at the third node, and causes the control signal to direct the charge pump circuit to cease the ramping of the voltage of the charge pump output signal if the voltage at the second node is at least equal to the voltage at the third node.