公开(公告)号：US20150077165A1

公开(公告)日：2015-03-19

申请号：US14485887

申请日：2014-09-15

Applicant: STMicroelectronics International N.V.

Inventor： Didier Harnay ,  Stephane Pineau ,  Francois Sittler

IPC: H03L7/107 ,  H03L7/08

CPC classification number: H03L7/1075 ,  H03L7/0802 ,  H04B15/04

Abstract: A method is for rejecting spurs within a chip containing analog and digital functions. The spurs may be timed by a clock signal derived from the output frequency of a high frequency phase locked loop. Original analog rejection bandwidths associated with operation of analog functions may be determined, and then original spurs associated with operation of the digital functions and capable of directly or indirectly affecting the original analog rejection bandwidths may be identified. A final analog rejection bandwidth may be determined based on the original analog rejection bandwidths, and final spurs may be obtained based on the original spurs. A frequency shift of the output frequency of the high frequency phase locked loop to effectuate a rejection of the final spurs from the final analog rejection bandwidth may be determined, and the high frequency phase locked loop may be controlled to shift the output frequency by the frequency shift.

Abstract translation: 一种方法是在包含模拟和数字功能的芯片中拒绝杂散。 杂散可以由从高频锁相环的输出频率导出的时钟信号定时。 可以确定与模拟功能的操作相关联的原始模拟拒绝带宽，然后可以识别与数字功能的操作相关联并能够直接或间接影响原始模拟拒绝带宽的原始杂散。 可以基于原始模拟拒绝带宽来确定最终的模拟拒绝带宽，并且可以基于原始杂散获得最终的杂散。 可以确定高频锁相环的输出频率的频移以实现最终模拟抑制带宽的最终杂散的抑制，并且可以控制高频锁相环以将输出频率移位频率 转移。

公开(公告)号：US09455729B2

公开(公告)日：2016-09-27

申请号：US14485887

申请日：2014-09-15

Applicant: STMicroelectronics International N.V.

Inventor： Didier Harnay ,  Stephane Pineau ,  Francois Sittler

IPC: H03L7/06 ,  H03L7/107 ,  H04B15/04 ,  H03L7/08

CPC classification number: H03L7/1075 ,  H03L7/0802 ,  H04B15/04

Abstract: A method is for rejecting spurs within a chip containing analog and digital functions. The spurs may be timed by a clock signal derived from the output frequency of a high frequency phase locked loop. Original analog rejection bandwidths associated with operation of analog functions may be determined, and then original spurs associated with operation of the digital functions and capable of directly or indirectly affecting the original analog rejection bandwidths may be identified. A final analog rejection bandwidth may be determined based on the original analog rejection bandwidths, and final spurs may be obtained based on the original spurs. A frequency shift of the output frequency of the high frequency phase locked loop to effectuate a rejection of the final spurs from the final analog rejection bandwidth may be determined, and the high frequency phase locked loop may be controlled to shift the output frequency by the frequency shift.

Abstract translation: 一种方法是在包含模拟和数字功能的芯片中拒绝杂散。 杂散可以由从高频锁相环的输出频率导出的时钟信号定时。 可以确定与模拟功能的操作相关联的原始模拟拒绝带宽，然后可以识别与数字功能的操作相关联并能够直接或间接影响原始模拟拒绝带宽的原始杂散。 可以基于原始模拟拒绝带宽来确定最终的模拟拒绝带宽，并且可以基于原始杂散获得最终的杂散。 可以确定高频锁相环的输出频率的频移以实现最终模拟抑制带宽的最终杂散的抑制，并且可以控制高频锁相环以将输出频率移位频率 转移。