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    Logic built-in self-test (LBIST) with pipeline scan enable launch on shift (LOS) flip-flop circuit
    2.
    发明授权
    Logic built-in self-test (LBIST) with pipeline scan enable launch on shift (LOS) flip-flop circuit 有权

    公开(公告)号：US10151797B2

    公开(公告)日：2018-12-11

    申请号：US15223061

    申请日：2016-07-29

    Applicant: STMicroelectronics International N.V.

    Inventor： Venkata Narayanan Srinivasan ,  Tripti Gupta

    IPC: G01R31/3185

    Abstract: A logic built-in self-test (LBIST) circuit implements a pipeline scan enable launch on shift (LOS) feature. A first scan chain flip-flop has a scan enable input configured to receive a first scan enable signal. A logic circuit has a first input coupled to a data output of the first scan chain flip-flop and a second input coupled to receive the first scan enable signal. A second scan chain flip-flop has a scan input coupled to a scan output of the first scan chain flip-flop. A scan enable input of the second scan chain flip-flop is coupled to receive a second scan enable signal generated at an output of the logic circuit. The first and second scan chain flip-flops are clocked by a same clock signal.

    SCAN CIRCUIT AND METHOD
    3.
    发明申请
    SCAN CIRCUIT AND METHOD 有权

    公开(公告)号：US20220244308A1

    公开(公告)日：2022-08-04

    申请号：US17164570

    申请日：2021-02-01

    Applicant: STMicroelectronics International N.V.

    Inventor： Venkata Narayanan Srinivasan ,  Shiv Kumar Vats ,  Tripti Gupta

    IPC: G01R31/3177 ,  G06F1/04 ,  G01R31/317

    Abstract: In an embodiment, a method for performing scan includes: entering scan mode; receiving a test pattern; applying the test pattern through a first scan chain by asserting and deasserting a scan enable signal to respectively perform shift and capture operations to the first scan chain; while applying the test pattern through the first scan chain, controlling a further scan flip-flop with the first scan chain without transitioning a further scan enable input of the further scan flip-flop; and evaluating an output of the first scan chain to detect faults.

    System and method for reducing voltage drop during automatic testing of integrated circuits
    5.
    发明授权
    System and method for reducing voltage drop during automatic testing of integrated circuits 有权
    集成电路自动测试时降低电压降的系统和方法

    公开(公告)号：US09222974B2

    公开(公告)日：2015-12-29

    申请号：US14152879

    申请日：2014-01-10

    Applicant: STMicroelectronics International N.V.

    Inventor： V Srinivasan ,  Satinder Singh Malhi ,  Tripti Gupta

    IPC: G01R31/3187 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/40

    CPC classification number: G01R31/31727 ,  G01R31/318552 ,  G01R31/318594 ,  G01R31/3187

    Abstract: A system and method for testing an integrated circuit using methodologies to reduce voltage drop during ATPG and LBIST testing. In one embodiment, delay elements may be added to a clock circuit used to generate the various clock signals that trigger the switching of the various electronic components. In another embodiment, logic circuitry may be added to a clock generation circuit to isolate clock domains in order to enable a clock signal in each clock domain in a specific pattern. In yet another embodiment, capture phases for LBIST testing may be made to be asynchrounous within each capture phase, such that data capture for one LBIST partition may be timed different from other capture phases for other LBIST partitions. Finally, a further embodiment ATPG circuitry may also be partitioned such that logic circuitry only enables one (or less than all) ATPG partition at a time.

    Abstract translation: 一种使用方法测试集成电路的系统和方法，以减少ATPG和LBIST测试期间的电压降。 在一个实施例中，可以将延迟元件添加到用于产生触发各种电子部件的切换的各种时钟信号的时钟电路。 在另一个实施例中，逻辑电路可以被添加到时钟发生电路以隔离时钟域，以便以特定模式启用每个时钟域中的时钟信号。 在又一个实施例中，用于LBIST测试的捕获阶段可以在每个捕获阶段内是不同步的，使得一个LBIST分区的数据捕获可以与其他LBIST分区的其他捕获阶段的时间不同。 最后，另外的实施例ATPG电路也可以被分割，使得逻辑电路一次只能启用一个（或少于所有）ATPG分区。

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