Dual clock edge triggered memory
    1.
    发明授权
    Dual clock edge triggered memory 有权
    双时钟边沿触发内存

    公开(公告)号:US08913457B2

    公开(公告)日:2014-12-16

    申请号:US14271165

    申请日:2014-05-06

    CPC classification number: G11C8/18 G11C7/1072 G11C7/22 G11C7/222

    Abstract: Memory circuitry includes memory components operable in response to first edges of an internal clock. The memory circuitry also includes internal clock generating circuitry to generate the internal clock in response to a system clock. The first edges of the internal clock are generated in response to both a rising and a falling edge of the system clock.

    Abstract translation: 存储器电路包括响应于内部时钟的第一边缘可操作的存储器组件。 存储电路还包括响应系统时钟产生内部时钟的内部时钟产生电路。 响应于系统时钟的上升沿和下降沿都产生内部时钟的第一个边沿。

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