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    Dual clock edge triggered memory
    1.
    发明授权
    Dual clock edge triggered memory 有权
    双时钟边沿触发内存

    公开(公告)号：US08913457B2

    公开(公告)日：2014-12-16

    申请号：US14271165

    申请日：2014-05-06

    Applicant: STMicroelectronics International N.V. ,  STMicroelectronics, SA

    Inventor： Nishu Kohli ,  Robin M. Wilson

    IPC: G11C8/00 ,  G11C8/18

    CPC classification number: G11C8/18 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222

    Abstract: Memory circuitry includes memory components operable in response to first edges of an internal clock. The memory circuitry also includes internal clock generating circuitry to generate the internal clock in response to a system clock. The first edges of the internal clock are generated in response to both a rising and a falling edge of the system clock.

    Abstract translation: 存储器电路包括响应于内部时钟的第一边缘可操作的存储器组件。 存储电路还包括响应系统时钟产生内部时钟的内部时钟产生电路。 响应于系统时钟的上升沿和下降沿都产生内部时钟的第一个边沿。

    Selective dual cycle write operation for a self-timed memory
    2.
    发明授权
    Selective dual cycle write operation for a self-timed memory 有权
    选择性的双周期写入操作为自定时存储器

    公开(公告)号：US09324414B2

    公开(公告)日：2016-04-26

    申请号：US13949449

    申请日：2013-07-24

    Applicant: STMicroelectronics International N.V.

    Inventor： Nishu Kohli ,  Shishir Kumar

    IPC: G11C8/16 ,  G11C11/419 ,  G11C7/22

    CPC classification number: G11C11/419 ,  G11C7/227

    Abstract: A write is performed to a first cell of a memory at a first row and column during a first memory access cycle. A memory access operation is made to a second cell at a second row and column during an immediately following second memory access cycle. If the memory access is a read from the second cell and the second row is the same as the first row, or if the memory access is a write to the second cell and the second row is the same as the first row and the second column is different than the first column, then a simultaneous operation is performed during the second memory access cycle. The simultaneous operation is an access of the second cell (for read or write) and a re-write of data from the first memory access cycle write operation back to the first cell.

    Abstract translation: 在第一存储器访问周期期间在第一行和列处对存储器的第一单元执行写入。 在紧接着的第二存储器访问周期期间，在第二行和列处对第二单元进行存储器存取操作。 如果存储器访问是从第二单元读取并且第二行与第一行相同，或者如果存储器访问是对第二单元的写入，并且第二行与第一行和第二列相同 与第一列不同，则在第二存储器访问周期期间执行同时操作。 同时操作是第二单元（用于读取或写入）的访问以及从第一存储器访问周期写入操作重新写入数据到第一单元。

    Programmable delay introducing circuit in self timed memory
    4.
    发明授权
    Programmable delay introducing circuit in self timed memory 有权
    自定时存储器中的可编程延迟引入电路

    公开(公告)号：US09147453B2

    公开(公告)日：2015-09-29

    申请号：US14532174

    申请日：2014-11-04

    Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

    Inventor： Nishu Kohli ,  Mudit Bhargava ,  Shishir Kumar

    IPC: H05B1/02 ,  G11C7/22 ,  G11C7/06 ,  G11C7/08 ,  G11C29/12 ,  G11C29/14 ,  G11C29/50

    CPC classification number: G11C7/227 ,  G11C7/06 ,  G11C7/08 ,  G11C7/22 ,  G11C7/222 ,  G11C29/12015 ,  G11C29/14 ,  G11C29/50 ,  G11C29/50012

    Abstract: Delays are introduced in self-timed memories by introducing a capacitance on the path of a signal to be delayed. The capacitances are realized by using idle-lying metal layers in the circuitry. The signal to be delayed is connected to the idle-lying capacitances via programmable switches. The amount of delay introduced depends on the capacitance introduced in the path of signal, which in turn depends on state of the switches. The state of the switches is controlled by delay codes provided externally to the delay introducing circuitry. Since idle-lying metal capacitances are utilized, the circuitry can be implemented using a minimum amount of additional hardware. Also, the delay provided by the circuitry is a function of memory cell SPICE characteristics and core parasitic capacitances.

    Abstract translation: 通过在要延迟的信号的路径上引入电容，在自定时存储器中引入延迟。 电容通过在电路中使用空闲的金属层来实现。 要延迟的信号通过可编程开关连接到空载电容。 引入的延迟量取决于在信号路径中引入的电容，这又取决于开关的状态。 开关的状态由延迟引入电路外部提供的延迟代码来控制。 由于利用空闲位置的金属电容，所以可以使用最小量的附加硬件实现电路。 此外，由电路提供的延迟是存储器单元SPICE特性和内核寄生电容的函数。

    SELECTIVE DUAL CYCLE WRITE OPERATION FOR A SELF-TIMED MEMORY
    5.
    发明申请
    SELECTIVE DUAL CYCLE WRITE OPERATION FOR A SELF-TIMED MEMORY 有权
    自定义存储器的选择性双循环写操作

    公开(公告)号：US20150029795A1

    公开(公告)日：2015-01-29

    申请号：US13949449

    申请日：2013-07-24

    Applicant: STMicroelectronics International N.V.

    Inventor： Nishu Kohli ,  Shishir Kumar

    IPC: G11C7/22

    CPC classification number: G11C11/419 ,  G11C7/227

    Abstract: A write is performed to a first cell of a memory at a first row and column during a first memory access cycle. A memory access operation is made to a second cell at a second row and column during an immediately following second memory access cycle. If the memory access is a read from the second cell and the second row is the same as the first row, or if the memory access is a write to the second cell and the second row is the same as the first row and the second column is different than the first column, then a simultaneous operation is performed during the second memory access cycle. The simultaneous operation is an access of the second cell (for read or write) and a re-write of data from the first memory access cycle write operation back to the first cell.

    Abstract translation: 在第一存储器访问周期期间在第一行和列处对存储器的第一单元执行写入。 在紧接着的第二存储器访问周期期间，在第二行和列处对第二单元进行存储器存取操作。 如果存储器访问是从第二单元读取并且第二行与第一行相同，或者如果存储器访问是对第二单元的写入，并且第二行与第一行和第二列相同 与第一列不同，则在第二存储器访问周期期间执行同时操作。 同时操作是第二单元（用于读取或写入）的访问以及从第一存储器访问周期写入操作重新写入数据到第一单元。

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