公开(公告)号：US20220137128A1

公开(公告)日：2022-05-05

申请号：US17083876

申请日：2020-10-29

申请人： STMicroelectronics International N.V. ,  STMicroelectronics Application GmbH ,  STMicroelectronics S.r.l.

发明人： Avneep Kumar GOYAL ,  Deepak BARANWAL ,  Thomas SZURMANT ,  Nicolas Bernard GROSSIER

IPC分类号： G01R31/317 ,  G01R31/3185

摘要： A testing tool includes a clock generation circuit generating a test clock and outputting the test clock via a test clock output pad, data processing circuitry clocked by the test clock, and data output circuitry receiving data output from the data processing circuitry and outputting the data via an input/output (IO) pad, the data output circuitry being clocked by the test clock. The testing tool also includes a programmable delay circuit generating a delayed version of the test clock, and data input circuitry receiving data input via the IO pad, the data input circuitry clocked by the delayed version of the test clock. The delayed version of the test clock is delayed to compensate for delay between transmission of a pulse of the test clock via the test clock output pad to an external computer and receipt of the data input from the external computer via the IO pad.

公开(公告)号：US20220308645A1

公开(公告)日：2022-09-29

申请号：US17702529

申请日：2022-03-23

申请人： STMicroelectronics Application GmbH ,  STMicroelectronics S.r.l.

发明人： Roberto COLOMBO ,  Nicolas Bernard GROSSIER

IPC分类号： G06F1/24

摘要： A processing system includes a reset circuit, a memory storing configuration data, and a hardware configuration circuit transmitting the configuration data to configuration data clients. The system executes a reset phase, configuration phase, and software runtime phase. First and second reset terminals are associated with first and second circuitries which are respectively associated with configuration data clients. The configuration data includes first and second mode configuration data for the first and second terminals. During the reset and configuration phase, the first circuitry activates a strong pull-down, and the second circuitry activates a weak pull-down. During the software runtime phase, the first circuitry activate a weak pull-down for implementing a bidirectional reset terminal or activates a weak pull-up resistance for implementing a reset output terminal, and the second circuitry activates a weak pull-up for implementing a reset input terminal or activates a strong pull-up for implementing a reset output terminal.

公开(公告)号：US20170315175A1

公开(公告)日：2017-11-02

申请号：US15221211

申请日：2016-07-27

申请人： STMICROELECTRONICS S.R.L.

发明人： Nicolas Bernard GROSSIER ,  Lorenzo GUERRIERI ,  Giuseppe Livio GOBBATO ,  Daniele ZERBINI ,  Martina CORDONI ,  Pasqualina Fragneto

IPC分类号： G01R31/317 ,  G01R31/3177

CPC分类号： G01R31/31713 ,  G01R31/28 ,  G01R31/3177 ,  G06F1/26 ,  G06F11/24 ,  G06F11/3024 ,  G06F11/3062 ,  G06F11/3636 ,  G06F11/364 ,  G06F11/3648 ,  G06F11/3656 ,  H02J13/0089 ,  H02J13/0093 ,  H02J13/0096 ,  H04B3/54 ,  H04B3/542 ,  H04B2203/5495 ,  H05B37/0263

摘要： A semiconductor device, for example an integrated circuit such as a microcontroller (MCU) or a digital signal processor (DSP), includes a semiconductor die coupled with a power supply line, a debug module coupled with the semiconductor die to exchange semiconductor die debug command and data signals with the semiconductor die, and a modem coupled with the power supply line. The debug module is arranged to convey the semiconductor die debug command and data signals over the power supply line.