公开(公告)号：US20040263217A1

公开(公告)日：2004-12-30

申请号：US10827675

申请日：2004-04-19

Applicant: STMicroelectronics Limited

Inventor： Matt Hutson ,  Andrew Dellow ,  Tom Ryan ,  Paul Elliott

IPC: H03K003/00

CPC classification number: G06F1/08

Abstract: A clock source selector for selecting either a first clock signal A or a second clock signal B in accordance with a switch request signal includes three retiming circuits each consisting of two clocked flip-flops. The switch request signal is first retimed relative to clock A to give a signal P, is then retimed relative to clock B to give a signal Q, and finally is retimed relative to clock A to give a signal R. Selector circuitry operates such that when signal Q is asserted, the second clock signal B is output, when neither signal P nor signal R, as combined by a NOR gate, are asserted, the first clock signal A is output, and at other times a zero level is output. The clock source selector can be used in an integrated circuit to form a glitch-free multiplexer.

公开(公告)号：US20020196710A1

公开(公告)日：2002-12-26

申请号：US10157731

申请日：2002-05-29

Applicant: STMicroelectronics Limited

Inventor： Andrew Dellow ,  Paul Elliott

IPC: G06F001/04 ,  G04F005/00

CPC classification number: G06F1/08

Abstract: A clock source selector for selecting either a first clock signal A or a second clock signal B in accordance with a switch request signal includes three retiming circuits each consisting of two clocked flip-flops. The switch request signal is first retimed relative to clock A to give a signal P, is then retimed relative to clock B to give a signal Q, and finally is retimed relative to clock A to give a signal R. Selector circuitry operates such that when signal Q is asserted, the second clock signal B is output, when neither signal P nor signal R, as combined by a NOR gate, are asserted, the first clock signal A is output, and at other times a zero level is output. The clock source selector can be used in an integrated circuit to form a glitch-free multiplexer.

Abstract translation: 用于根据切换请求信号选择第一时钟信号A或第二时钟信号B的时钟源选择器包括三个重新定时电路，每个由两个时钟触发器组成。 开关请求信号相对于时钟A首先被重新定时以给出信号P，相对于时钟B被重新定时以给出信号Q，并且最后相对于时钟A被重新定时以给出信号R.选择器电路操作使得当 信号Q被置位，当第二时钟信号B被输出时，当由或非门组合的信号P和信号R都不被断言时，输出第一时钟信号A，并且在其它时间输出零电平。 时钟源选择器可用于集成电路中以形成无毛刺多路复用器。