公开(公告)号：US20030185067A1

公开(公告)日：2003-10-02

申请号：US10354908

申请日：2003-01-30

Applicant: STMicroelectronics Limited

Inventor： Andrew Dellow

IPC: G11C007/00

CPC classification number: G06F13/28

Abstract: A semiconductor integrated circuit for use in direct memory access (DMA) has two sources which communicate with a bus through a bus interface. A DMA access signal generator is coupled to the bus interface and asserts a DMA access output signal at a DMA access signal pin whenever either of the sources requires a DMA access. The need for separate DMA access signal pins for each of the two sources is thereby avoided. With targets on two separate integrated circuits, a single DMA access pin can be used for the two targets, while chip select signals at chip select pins on the source integrated circuit indicate which of the two targets is intended for the DMA access.

Abstract translation: 用于直接存储器访问（DMA）的半导体集成电路具有通过总线接口与总线通信的两个源。 DMA访问信号发生器耦合到总线接口，并且每当任何一个源需要DMA访问时，在DMA访问信号引脚处断言DMA访问输出信号。 因此避免了对于两个源中的每一个的单独的DMA访问信号引脚的需要。 通过两个独立的集成电路上的目标，两个目标可以使用单个DMA访问引脚，而源集成电路芯片选择引脚上的芯片选择信号指示两个目标中的哪一个用于DMA访问。

公开(公告)号：US20040263217A1

公开(公告)日：2004-12-30

申请号：US10827675

申请日：2004-04-19

Applicant: STMicroelectronics Limited

Inventor： Matt Hutson ,  Andrew Dellow ,  Tom Ryan ,  Paul Elliott

IPC: H03K003/00

CPC classification number: G06F1/08

Abstract: A clock source selector for selecting either a first clock signal A or a second clock signal B in accordance with a switch request signal includes three retiming circuits each consisting of two clocked flip-flops. The switch request signal is first retimed relative to clock A to give a signal P, is then retimed relative to clock B to give a signal Q, and finally is retimed relative to clock A to give a signal R. Selector circuitry operates such that when signal Q is asserted, the second clock signal B is output, when neither signal P nor signal R, as combined by a NOR gate, are asserted, the first clock signal A is output, and at other times a zero level is output. The clock source selector can be used in an integrated circuit to form a glitch-free multiplexer.

公开(公告)号：US20040223618A1

公开(公告)日：2004-11-11

申请号：US10773089

申请日：2004-02-03

Applicant: STMicroelectronics Limited

Inventor： Andrew Dellow

IPC: H04L009/00

CPC classification number: H04L9/0631 ,  H04L9/0827 ,  H04L2209/601

Abstract: A semiconductor integrated circuit having a plurality of selectable pathways inter-connected to data sources and data destinations; a cryptographic circuit connected to the selectable pathways to selectively receive data from at least one of the data sources, to decrypt or encrypt the data in accordance with a key, and to selectively provide the encrypted or decrypted data to at least one of the data destinations; an instruction interpreter arranged to receive an instruction signal and to generate an output to control the plurality of selectable pathways to select from which of the data sources the cryptographic circuit receives data and to which destination the cryptographic circuit provides data. The instruction interpreter configured such that the instruction signal defines a data pathway that operates in accordance with a rule that limits the data pathway configurations which are selectable.

Abstract translation: 一种具有与数据源和数据目的地相互连接的多个可选路径的半导体集成电路; 连接到所述可选择路径以选择性地从所述数据源中的至少一个数据源接收数据的密码电路，根据密钥对所述数据进行解密或加密，并且选择性地将加密或解密的数据提供给所述数据目的地中的至少一个 ; 指令解释器，被布置为接收指令信号并产生输出以控制多个可选路径，以从密码电路中的哪一个数据源接收数据以及加密电路提供数据的哪个目的地。 指令解释器被配置为使得指令信号定义根据限制可选择的数据路径配置的规则操作的数据通路。

公开(公告)号：US20030182570A1

公开(公告)日：2003-09-25

申请号：US10354891

申请日：2003-01-30

Applicant: STMicroelectronics Limited

Inventor： Andrew Dellow

IPC: G06F011/30

CPC classification number: G06F21/575 ,  G06F21/64

Abstract: A semiconductor integrated circuit includes a processor for executing application code from a memory and a verifier processor arranged to receive the application code via the same internal bus as the processor. The verifier processor performs a verification function to check that the application code is authentic. The verifier processor runs autonomously and cannot be spoofed as it receives the application code via the same internal bus as the main processor.

Abstract translation: 半导体集成电路包括用于从存储器执行应用代码的处理器和被布置为经由与处理器相同的内部总线接收应用代码的验证器处理器。 验证者处理器执行验证功能以检查应用代码是否可信。 验证者处理器自动运行，并且不能通过与主处理器相同的内部总线接收应用代码而被欺骗。

公开(公告)号：US20020196710A1

公开(公告)日：2002-12-26

申请号：US10157731

申请日：2002-05-29

Applicant: STMicroelectronics Limited

Inventor： Andrew Dellow ,  Paul Elliott

IPC: G06F001/04 ,  G04F005/00

CPC classification number: G06F1/08

Abstract: A clock source selector for selecting either a first clock signal A or a second clock signal B in accordance with a switch request signal includes three retiming circuits each consisting of two clocked flip-flops. The switch request signal is first retimed relative to clock A to give a signal P, is then retimed relative to clock B to give a signal Q, and finally is retimed relative to clock A to give a signal R. Selector circuitry operates such that when signal Q is asserted, the second clock signal B is output, when neither signal P nor signal R, as combined by a NOR gate, are asserted, the first clock signal A is output, and at other times a zero level is output. The clock source selector can be used in an integrated circuit to form a glitch-free multiplexer.

Abstract translation: 用于根据切换请求信号选择第一时钟信号A或第二时钟信号B的时钟源选择器包括三个重新定时电路，每个由两个时钟触发器组成。 开关请求信号相对于时钟A首先被重新定时以给出信号P，相对于时钟B被重新定时以给出信号Q，并且最后相对于时钟A被重新定时以给出信号R.选择器电路操作使得当 信号Q被置位，当第二时钟信号B被输出时，当由或非门组合的信号P和信号R都不被断言时，输出第一时钟信号A，并且在其它时间输出零电平。 时钟源选择器可用于集成电路中以形成无毛刺多路复用器。

公开(公告)号：US20020191725A1

公开(公告)日：2002-12-19

申请号：US10106899

申请日：2002-03-25

Applicant: STMicroelectronics Limited

Inventor： Andrew Dellow

IPC: H03D003/24

CPC classification number: H03D13/004

Abstract: A digital phase comparator circuit that determines and adjusts the relative phase of two digital clock signals derived from the same digital clock. The circuit having two inputs, one connected to receive each of the clock signals to be compared and including a latch circuit to receive one clock signal at the clock input, and the other clock signal at a data input. The latch circuit is arranged so that the output is equal to the signal at the data input when measured at the clock edge. The output is therefore a logic null1null when the second clock leads the first clock, and a logic null0null when the second clock lags the first clock.

Abstract translation: 数字相位比较器电路，用于确定并调整从相同数字时钟导出的两个数字时钟信号的相对相位。 该电路具有两个输入端，一个连接到接收要比较的每个时钟信号，并且包括用于在时钟输入端接收一个时钟信号的锁存电路，以及数据输入端的另一个时钟信号。 锁存电路被布置为使得当在时钟边沿测量时，输出等于数据输入端的信号。 因此，当第二个时钟引导第一个时钟时，输出为逻辑“1”，当第二个时钟延迟第一个时钟时，输出为逻辑“0”。

公开(公告)号：US20040156507A1

公开(公告)日：2004-08-12

申请号：US10705782

申请日：2003-11-10

Applicant: STMicroelectronics Limited

Inventor： Andrew Dellow ,  Rodrigo Cordero

IPC: H04L009/00

CPC classification number: H04N21/42623 ,  H04N21/26613 ,  H04N21/4623

Abstract: A semiconductor integrated circuit for the processing of conditional access television signals, the circuit including an input interface for receiving encrypted television signals and an output interface for output of decrypted television signals. Control signals broadcast with the television signals include control words and common keys. The common keys are received in encrypted form, encrypted according to a secret key unique to each semiconductor integrated circuit. The input interface is connected to a decryption circuit whereby the only manner of providing the common keys to the circuit are in encrypted form encrypted according to the secret key. Due to the monolithic nature of the circuit, no secrets are exposed and the system is secure.

Abstract translation: 一种用于处理条件接收电视信号的半导体集成电路，该电路包括用于接收加密的电视信号的输入接口和用于输出解密的电视信号的输出接口。 用电视信号广播的控制信号包括控制字和公共密钥。 公共密钥以加密形式接收，根据每个半导体集成电路独有的秘密密钥进行加密。 输入接口连接到解密电路，由此向电路提供公共密钥的唯一方式是根据密钥加密的加密形式。 由于电路的整体性质，没有暴露的秘密和系统是安全的。

公开(公告)号：US20020171459A1

公开(公告)日：2002-11-21

申请号：US10104994

申请日：2002-03-22

Applicant: STMicroelectronics Limited

Inventor： Andrew Dellow

IPC: H03K021/00

CPC classification number: H03K23/68 ,  H03K23/546

Abstract: A digital frequency divider includes phase control of the output signal in increments of whole or half cycles of the input frequency. Whole cycle phase control is achieved by varying (logically or physically) the tap off point of a shift register loaded with a bit pattern for appropriate division. Half cycle phase changes are achieved by a multiplexer selecting one of two signals every half cycle.

Abstract translation: 数字分频器包括以输入频率的整个或半个周期为增量的输出信号的相位控制。 通过改变（逻辑上或物理上）通过加载位模式的移位寄存器的抽头点进行适当划分来实现整个周期相位控制。 半周期相位变化通过多路复用器每半周期选择两个信号之一来实现。