公开(公告)号：US11848378B2

公开(公告)日：2023-12-19

申请号：US17373198

申请日：2021-07-12

Applicant: STMicroelectronics Pte Ltd

Inventor： Ditto Adnan ,  Maurizio Gabriele Castorina ,  Voon Cheng Ngwan ,  Fadhillawati Tahir

IPC: H01L29/78 ,  H01L21/765 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L21/765 ,  H01L29/401 ,  H01L29/407 ,  H01L29/66734

Abstract: A semiconductor substrate has a trench extending from a front surface and including a lower part and an upper part. A first insulation layer lines the lower part of the trench, and a first conductive material in the lower part is insulated from the semiconductor substrate by the first insulating layer to form a field plate electrode of a transistor. A second insulating layer lines sidewalls of the upper part of said trench. A third insulating layer lines a top surface of the first conductive material at a bottom of the upper part of the trench. A second conductive material fills the upper part of the trench. The second conductive material forms a gate electrode of the transistor that is insulated from the semiconductor substrate by the second insulating layer and further insulated from the first conductive material by the third insulating layer.

公开(公告)号：US12224342B2

公开(公告)日：2025-02-11

申请号：US17694276

申请日：2022-03-14

Applicant: STMicroelectronics Pte Ltd

Inventor： Yean Ching Yong ,  Maurizio Gabriele Castorina ,  Voon Cheng Ngwan ,  Ditto Adnan ,  Fadhillawati Tahir ,  Churn Weng Yim

IPC: H01L29/78 ,  H01L21/764 ,  H01L21/765 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66

Abstract: An integrated circuit transistor device includes a semiconductor substrate providing a drain, a first doped region buried in the semiconductor substrate providing a body and a second doped region in the semiconductor substrate providing a source. A trench extends into the semiconductor substrate and passes through the first and second doped regions. An insulated polygate region within the trench surrounds a polyoxide region that may have void inclusion. The polygate region is formed by a first gate lobe and second gate lobe on opposite sides of the polyoxide region. A pair of gate contacts are provided at each trench. The pair of gate contacts includes: a first gate contact extending into the first gate lobe at a location laterally offset from the void and a second gate contact extending into the second gate lobe at a location laterally offset from the void.