公开(公告)号：US20040155689A1

公开(公告)日：2004-08-12

申请号：US10739879

申请日：2003-12-18

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Manoj Kumar ,  Rajesh Narwal

IPC: H03K003/037

CPC classification number: H03K3/3565

Abstract: A differential input receiver with hysteresis on both sides of the reference voltage may include a two-input, one-output differential amplifier including two input transistors having a common terminal connected together. The control terminal of each transistor may be connected to one of the inputs of the differential amplifier. The output of the differential amplifier may be connected to a set of cascaded digital inverters/buffers, and an output of each digital buffer may be connected to the control terminal of a feedback transistor. The feedback transistor may be connected in parallel across each of the input transistors so that when one input voltage increases above or decreases below the input voltage at the second input by a predetermined threshold value, the feedback transistors operate to provide positive feedback to facilitate a rapid switching action at the output.

Abstract translation: 具有参考电压两侧的迟滞的差分输入接收器可以包括双输入单输出差分放大器，其包括连接在一起的共同端子的两个输入晶体管。 每个晶体管的控制端可以连接到差分放大器的一个输入端。 差分放大器的输出可以连接到一组级联的数字反相器/缓冲器，并且每个数字缓冲器的输出可以连接到反馈晶体管的控制端子。 反馈晶体管可以并联连接在每个输入晶体管上，使得当一个输入电压在第二输入处增加到或低于第二输入处的输入电压以下预定阈值时，反馈晶体管操作以提供正反馈以促进快速 在输出端切换动作。

公开(公告)号：US20040061524A1

公开(公告)日：2004-04-01

申请号：US10611322

申请日：2003-07-01

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Manoj Kumar ,  Sunil Chandra Kasanyal

IPC: H03K019/0175

CPC classification number: H03K19/018521

Abstract: A voltage level translator for digital logic circuits provides high level to low level voltage translation with equal rise and fall delays. The voltage level translator may include an input high voltage logic inverter (operating at the high voltage level) and connected to an output low voltage logic inverter operating at the low voltage level via a voltage reduction circuit. A related method for providing high level to low voltage translation may include providing an input inverter operating at the high voltage level and an output inverter operating at the low voltage level. Furthermore, the output of the high voltage inverter may be coupled to the input of the low voltage inverter after reducing the output voltage of the high voltage inverter to the required level.

Abstract translation: 用于数字逻辑电路的电压电平转换器具有相同的上升和下降延迟的高电平到低电平电压转换。 电压电平转换器可以包括输入高压逻辑逆变器（以高电压电平工作），并通过电压降低电路连接到在低电压电平下工作的输出低压逻辑逆变器。 用于提供高电平到低电压平移的相关方法可以包括提供在高电压电平下工作的输入逆变器和在低电压电平下工作的输出逆变器。 此外，在将高压逆变器的输出电压降低到所需水平之后，高压逆变器的输出可以耦合到低压逆变器的输入。

公开(公告)号：US20040032284A1

公开(公告)日：2004-02-19

申请号：US10460044

申请日：2003-06-12

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Manoj Kumar

IPC: H03K019/0175

CPC classification number: H03K19/018521

Abstract: A voltage level translator for digital logic circuits provides high level to low level voltage translation with equal rise and fall delays. The voltage level translator may include an input high voltage logic inverter (operating at the high voltage level) and connected to an output low voltage logic inverter operating at the low voltage level via a voltage reduction circuit. A related method for providing high level to low voltage translation may include providing an input inverter operating at the high voltage level and an output inverter operating at the low voltage level. Furthermore, the output of the high voltage inverter may be coupled to the input of the low voltage inverter after reducing the output voltage of the high voltage inverter to the required level.