公开(公告)号：US20030172363A1

公开(公告)日：2003-09-11

申请号：US10347139

申请日：2003-01-17

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Rajat Chauhan ,  Rajesh Kaushik

IPC: G06F017/50

CPC classification number: H03K19/17748 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744

Abstract: A method and an improved FPGA apparatus for enabling the selective deployment of unused flip-flops or other circuit elements in IO cells and unused decoders or other circuit elements in Look Up Tables (LUT), for core logic functions is provided, comprising disconnecting means for selectively disconnecting unused circuit elements from the IO pad circuitry or from said LUT circuitry, and connecting means for selectively connecting said disconnected circuit elements either to the connection matrix of the core logic or between themselves to provide independently configured functions.

Abstract translation: 提供了一种方法和改进的FPGA装置，用于在核心逻辑功能中使得能够选择性地部署IO单元中的未使用的触发器或其他电路元件以及查找表（LUT）中的未使用的解码器或其他电路元件，包括用于 有选择地从IO垫电路或所述LUT电路断开未使用的电路元件，以及连接装置，用于选择性地将所述断开的电路元件连接到核心逻辑的连接矩阵或它们之间，以提供独立配置的功能。