公开(公告)号：US20040070422A1

公开(公告)日：2004-04-15

申请号：US10608854

申请日：2003-06-27

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Sushma Mohan ,  Parvesh Swami

IPC: H03K019/177

CPC classification number: H03K19/17728 ,  H03K19/1737

Abstract: A Programmable Logic Device (PLD) incorporating a plurality of Programmable Logic Blocks (PLBS) providing enhanced flexibility for Cascade logic functions, each comprising a multi-input Look Up Table (LUT) providing one input to a Cascade Logic block for implementing desired Cascade Logic functions. The other input of the Cascade Logic block is a Cascade-In signal. A 2-input selection multiplexer receives one input from the output of the Cascade Logic block and the other from the output of the LUT for selecting either the Cascade Logic output or the LUT output as the unregistered output. The arrangement is such that the Cascade output and the multiplexer output are simultaneously available from the PLB.

Abstract translation: 一种包含多个可编程逻辑块（PLBS）的可编程逻辑器件（PLD），其为级联逻辑功能提供增强的灵活性，每个逻辑器件包括多输入查找表（LUT），其为级联逻辑块提供一个输入，以实现所需的级联逻辑 功能。 级联逻辑块的另一个输入是级联输入信号。 2输入选择多路复用器从串级逻辑块的输出接收一个输入，而从LUT的输出接收另一个输入，用于选择级联逻辑输出或LUT输出作为未注册输出。 这种布置使得级联输出和多路复用器输出可以从PLB同时获得。