公开(公告)号：US20040008549A1

公开(公告)日：2004-01-15

申请号：US10440043

申请日：2003-05-15

Applicant: STMicroelectronics S.r.I

Inventor： Rino Micheloni ,  Aldo Losavio

IPC: G11C007/00

CPC classification number: G11C29/82 ,  G11C29/846

Abstract: The memory device has a memory block, formed by a plurality of standard sectors and a redundancy portion; a control circuit, which controls programming and erasing of the data of the memory cells; and a correctness verifying circuit for the data stored in the memory cells. The correctness verifying circuit is enabled by the control circuit and generates an incorrect-datum signal in the event of detection of at least one non-functioning cell. The control circuit moreover activates redundancy, enabling the redundancy portion and storing redundancy data in a redundancy-memory stage in the presence of an incorrect datum. Various solutions are presented that implement column, row and sector redundancy, both in case of erasing and programming.

Abstract translation: 存储装置具有由多个标准扇区和冗余部分形成的存储块; 控制电路，其控制存储器单元的数据的编程和擦除; 以及用于存储在存储单元中的数据的正确性验证电路。 正确性验证电路由控制电路启用，并且在检测至少一个非功能单元的情况下产生不正确的基准信号。 此外，控制电路激活冗余，使冗余部分能够在存在不正确的数据的情况下将冗余数据存储在冗余存储器级中。 提出了实现列，行和扇区冗余的各种解决方案，无论在擦除和编程的情况下。