公开(公告)号：US20030147290A1

公开(公告)日：2003-08-07

申请号：US10334126

申请日：2002-12-30

Applicant: STMicroelectronics S.r.I.

Inventor： Rino Micheloni ,  Giovanni Campardo

IPC: G11C007/00

CPC classification number: G11C11/5621 ,  G11C8/14 ,  G11C11/56 ,  G11C16/08 ,  G11C16/30

Abstract: A power supply circuit structure is useful with a row decoder for reading/writing data from/into memory cells of an integrated electrically programmable/erasable non-volatile memory device incorporating an array of multilevel memory cells. Advantageously, multiple supply voltages to the row decoder and a switching circuit for transferring the voltages over hierarchic-mode enabled conduction paths are provided.

Abstract translation: 电源电路结构对于包含多层存储器单元阵列的集成电可编程/可擦除非易失性存储器件的/从存储单元读/写数据的行解码器是有用的。 有利地，提供了对行解码器的多个电源电压和用于将电压传送到分层模式使能的传导路径的开关电路。

公开(公告)号：US20030142547A1

公开(公告)日：2003-07-31

申请号：US10331106

申请日：2002-12-27

Applicant: STMicroelectronics S.r.I.

Inventor： Rino Micheloni ,  Ilaria Motta

IPC: G11C011/34

CPC classification number: G11C16/30

Abstract: A method and a circuit are for regulating the source terminal voltage of a non-volatile memory cell during the cell programming and/or reading phases. The method includes a phase of locally regulating the voltage value and includes comparing the source current of the cell array with a reference current. A fraction of the source current is converted to a voltage and compared with a voltage generated from a memory cell acting as a reference and being programmed to the distribution with the highest current levels. The comparison may be used for controlling a current generator to inject, into the source terminal, the current necessary to keep the predetermined voltage thereof at a constant value.

Abstract translation: 一种方法和电路用于在单元编程和/或读取阶段期间调节非易失性存储单元的源极端子电压。 该方法包括局部调节电压值的相位，并且包括将电池阵列的源电流与参考电流进行比较。 将源电流的一部分转换成电压，并将其与作为参考的存储器单元产生的电压进行比较，并将其编程为具有最高电流电平的分布。 比较可以用于控制电流发生器向源极端子注入将其预定电压保持在恒定值所需的电流。

公开(公告)号：US20020122340A1

公开(公告)日：2002-09-05

申请号：US10002599

申请日：2001-10-31

Applicant: STMicroelectronics S.r.I

Inventor： Rino Micheloni ,  Andrea Sacco

IPC: G11C016/04

CPC classification number: G11C16/24 ,  G11C16/10

Abstract: A pulse programming method for a non-volatile memory device includes: addressing memory cells to be programmed within the device by selecting corresponding hierarchic decoder transistors; biasing the gate terminals of the memory cells; and programming the memory cells by applying a voltage pulse, regulated by a bias circuit, to the drain terminals of the memory cells. Advantageously, the programming method further comprises a step of precharging an internal node of the bias circuit before starting the programming step, the internal node being connected to a parasitic capacitance of the memory device.

Abstract translation: 一种用于非易失性存储器件的脉冲编程方法包括：通过选择相应的层级解码器晶体管寻址要在器件内编程的存储器单元; 偏置存储单元的栅极端子; 以及通过将由偏置电路调节的电压脉冲施加到存储器单元的漏极端子来对存储器单元进行编程。 有利地，编程方法还包括在开始编程步骤之前对偏置电路的内部节点进行预充电的步骤，内部节点连接到存储器件的寄生电容。

公开(公告)号：US20020048187A1

公开(公告)日：2002-04-25

申请号：US09972726

申请日：2001-10-04

Applicant: STMicroelectronics S.r.I.

Inventor： Andrea Pierin ,  Stefano Gregori ,  Rino Micheloni ,  Osama Khouri ,  Guido Torelli

IPC: G11C011/34

CPC classification number: G11C16/30 ,  G11C5/145 ,  G11C7/06 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/26

Abstract: A multilevel nonvolatile memory includes a supply line supplying a supply voltage, a voltage boosting circuit supplying a boosted voltage, higher than the supply voltage, a boosted line connected to the voltage boosting circuit and a reading circuit including at least one comparator. The comparator includes a first and a second input, a first and a second output, at least one amplification stage connected to the boosted line, and a boosted line latch stage connected to the supply line.

Abstract translation: 多级非易失性存储器包括提供电源电压的电源线，提供高于电源电压的升压电压的升压电路，连接到升压电路的升压线路和包括至少一个比较器的读取电路。 比较器包括第一和第二输入，第一和第二输出，连接到升压线路的至少一个放大级和连接到电源线的升压线路锁存级。

公开(公告)号：US20040230869A1

公开(公告)日：2004-11-18

申请号：US10805182

申请日：2004-03-19

Applicant: STMicroelectronics S.r.I.

Inventor： Rino Micheloni ,  Roberto Ravasio

IPC: H05K010/00

CPC classification number: G06F11/1068 ,  G06F11/1048

Abstract: An embodiment of the present invention relates to an integrated memory system comprising at least a non-volatile memory and an automatic storage error corrector, and wherein the memory is connected to a controller by means of an interface bus. Advantageously, the system comprises in the memory circuit means, functionally independent, each being responsible for the correction of a predetermined storage error; at least one of said means generating a signal to ask a correction being external to the memory.

Abstract translation: 本发明的实施例涉及至少包括非易失性存储器和自动存储错误校正器的集成存储器系统，并且其中存储器通过接口总线连接到控制器。 有利地，该系统在存储器电路装置中包括功能上独立的，每个都负责校正预定的存储错误; 所述装置中的至少一个产生要求校正在存储器外部的信号。

公开(公告)号：US20040136242A1

公开(公告)日：2004-07-15

申请号：US10614693

申请日：2003-07-07

Applicant: STMicroelectronics S.r.I.

Inventor： Rino Micheloni ,  Ilaria Motta ,  Marco Capovilla

IPC: G11C005/00

CPC classification number: G11C16/12 ,  G11C5/145 ,  G11C8/08 ,  G11C2207/2227

Abstract: Voltage booster device (3) such as to selectively assume an active status and a stand-by status, said device comprising: a first terminal (15) such as to assume a respective electric potential and associated to a first capacitor (16), a second terminal (10) associated to a second capacitor (11) and selectively connectable to the first terminal (15), characterised in that it also comprises circuital means (100) for discharging the first capacitor thus reducing in module the electrical potential of the first terminal (15), the circuital means being activated to functioning when said device in the stand-by status and the second terminal (10) is disconnected from said first terminal (15).

Abstract translation: 电压升压装置（3），例如选择性地呈现活动状态和待机状态，所述装置包括：第一端子（15），以便呈现相应的电位并与第一电容器（16）相关联， 与第二电容器（11）相关并且可选择地连接到第一端子（15）的第二端子（10），其特征在于，其还包括用于对第一电容器进行放电的电路装置（100），从而减少模块中的第一电容器 当所述处于待机状态的设备和所述第二终端（10）与所述第一终端（15）断开连接时，所述电路装置被激活以起作用。

公开(公告)号：US20040008549A1

公开(公告)日：2004-01-15

申请号：US10440043

申请日：2003-05-15

Applicant: STMicroelectronics S.r.I

Inventor： Rino Micheloni ,  Aldo Losavio

IPC: G11C007/00

CPC classification number: G11C29/82 ,  G11C29/846

Abstract: The memory device has a memory block, formed by a plurality of standard sectors and a redundancy portion; a control circuit, which controls programming and erasing of the data of the memory cells; and a correctness verifying circuit for the data stored in the memory cells. The correctness verifying circuit is enabled by the control circuit and generates an incorrect-datum signal in the event of detection of at least one non-functioning cell. The control circuit moreover activates redundancy, enabling the redundancy portion and storing redundancy data in a redundancy-memory stage in the presence of an incorrect datum. Various solutions are presented that implement column, row and sector redundancy, both in case of erasing and programming.

Abstract translation: 存储装置具有由多个标准扇区和冗余部分形成的存储块; 控制电路，其控制存储器单元的数据的编程和擦除; 以及用于存储在存储单元中的数据的正确性验证电路。 正确性验证电路由控制电路启用，并且在检测至少一个非功能单元的情况下产生不正确的基准信号。 此外，控制电路激活冗余，使冗余部分能够在存在不正确的数据的情况下将冗余数据存储在冗余存储器级中。 提出了实现列，行和扇区冗余的各种解决方案，无论在擦除和编程的情况下。

公开(公告)号：US20030151949A1

公开(公告)日：2003-08-14

申请号：US10331116

申请日：2002-12-27

Applicant: STMicroelectronics S.r.I.

Inventor： Rino Micheloni ,  Sabina Mognoni ,  Ilaria Motta ,  Andrea Sacco

IPC: G11C011/34

CPC classification number: G11C16/30

Abstract: A method and program-load circuit is for regulating the voltages at the drain and body terminals of a non-volatile memory cell being programmed. These voltages are applied from a program-load circuit connected in a conduction pattern to transfer a predetermined voltage value to at least one terminal of the memory cell. The method includes a step of regulating the voltage value locally, within the program-load circuit, to overcome the effect of a parasitic resistor present in the conduction pattern.

Abstract translation: 一种方法和程序加载电路用于调节正被编程的非易失性存储单元的漏极和体端子处的电压。 这些电压从连接在导通图案中的编程负载电路施加，以将预定的电压值传送到存储单元的至少一个端子。 该方法包括在编程负载电路内局部调节电压值以克服存在于导电图案中的寄生电阻的影响的步骤。

公开(公告)号：US20030028709A1

公开(公告)日：2003-02-06

申请号：US10159780

申请日：2002-05-30

Applicant: STMicroelectronics S.r.I.

Inventor： Rino Micheloni ,  Giovanni Campardo ,  Salvatrice Scommegna

IPC: G06F012/00

CPC classification number: G11C16/344 ,  G11C16/3436

Abstract: Described herein is an erase method for an electrically erasable nonvolatile memory device, in particular an EEPROM-FLASH nonvolatile memory device, comprising a memory array formed by a plurality of memory cells arranged in rows and columns and grouped in sectors each formed by a plurality of subsectors, which are in turn formed by one or more rows. Erase of the memory array is performed by sectors and for each sector envisages applying an erase pulse to the gate terminals of all the memory cells of the sector, verifying erase of the memory cells of each subsector, and applying a further erase pulse to the gate terminals of the memory cells of only the subsectors that are not completely erased.

Abstract translation: 这里描述了一种用于电可擦除非易失性存储器件，特别是EEPROM闪存非易失性存储器件的擦除方法，其特征在于包括由排列成行和列的多个存储单元形成的存储器阵列， 子行业，其又由一行或多行形成。 存储器阵列的擦除由扇区执行，并且对于每个扇区，设想对扇区的所有存储器单元的栅极端子施加擦除脉冲，验证每个子部件的存储器单元的擦除，以及向栅极施加另外的擦除脉冲 只有子部分的存储器单元的端子不被完全擦除。

公开(公告)号：US20040208063A1

公开(公告)日：2004-10-21

申请号：US10675221

申请日：2003-09-30

Applicant: STMicroelectronics S.r.I.

Inventor： Rino Micheloni ,  Giovanni Campardo

IPC: G11C011/34 ,  G11C016/04

CPC classification number: G11C29/82 ,  G11C16/04 ,  G11C16/16 ,  G11C29/44 ,  G11C2029/1208

Abstract: The invention relates to a method for erasing non-volatile memory cells, and to a corresponding non-volatile memory device of the programmable and electrically erasable type implementing the method, and comprising a memory cell array organized in a row-and-column layout, and divided in array sectors, including at least one row decode circuit portion being supplied positive and negative voltages. The method is applied whenever the issue of the erase algorithm is negative, and comprises the following steps: forcing an incompletely erased sector into a read condition; scanning the rows of said sector to check for the possible presence of a spurious current indicating a fail state; identifying and electrically isolating the failed row; re-addressing from said failed row to a redundant row provided in the same sector; re-starting the erase algorithm.

Abstract translation: 本发明涉及一种用于擦除非易失性存储单元的方法，以及实现该方法的可编程和电可擦除类型的相应非易失性存储器件，并且包括以行和列布局组织的存储单元阵列， 并且被划分成阵列扇区，包括至少一个行解码电路部分被提供正和负电压。 每当擦除算法的问题为负时，该方法被应用，并且包括以下步骤：强制将未完全擦除的扇区进入读取状态; 扫描所述扇区的行以检查指示故障状态的寄生电流的可能存在; 识别和电隔离失败的行; 从所述故障行重新寻址到在同一扇区中提供的冗余行; 重新启动擦除算法。