公开(公告)号：US20020018390A1

公开(公告)日：2002-02-14

申请号：US09909467

申请日：2001-07-19

Applicant: STMicroelectronics S.r.I.

Inventor： Emanuele Confalonieri ,  Lorenzo Bedarida ,  Mauro Sali ,  Simone Bartoli

IPC: G11C005/14

CPC classification number: G11C16/30

Abstract: A semiconductor memory includes a plurality of memory cells connected to one another to form a matrix of memory cells. A charge pump is connected to the matrix of memory cells. A plurality of controllable connection elements are provided, with each controllable connection element connected between an output terminal of the charge pump and a respective column line. Connected to the output of the charge pump is the series connection of a first element equivalent to a controllable connection element, and a second element equivalent to a memory cell in a predetermined biasing condition. A voltage regulator is connected between the second equivalent element and the input terminal of the charge pump for regulating the output voltage therefrom based upon a voltage present between terminals of the second equivalent element.

公开(公告)号：US20040190336A1

公开(公告)日：2004-09-30

申请号：US10724023

申请日：2003-11-26

Applicant: STMicroelectronics S.r.I

Inventor： Emanuele Confalonieri ,  Antonio Geraci ,  Vincenzo Dima ,  Nicola Del Gatto

IPC: G11C011/34

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621

Abstract: A method for management of the programming controls in a multilevel device is provided. During the control step cells are not controlled all together but they are conveniently selected in order to reduce the source resistance and consumption effect, but without penalizing change times.

Abstract translation: 提供了一种用于管理多电平设备中的编程控制的方法。 在控制步骤期间，电池不能全部控制，但是它们方便地选择，以便降低电源电阻和消耗效应，但不影响变化时间。

公开(公告)号：US20030149831A1

公开(公告)日：2003-08-07

申请号：US10331177

申请日：2002-12-27

Applicant: STMicroelectronics S.r.I.

Inventor： Emanuele Confalonieri ,  Marco Sforzin

IPC: G06F012/00

CPC classification number: G06F11/1072

Abstract: A decoding structure for a memory device with a control code is used in a memory including a matrix of memory cells grouped into pages to each of which a block of control information is associated, and a plurality of reading elements for reading a plurality of pages in parallel. The decoding structure selectively connects each reading element to a plurality of memory cells, and selectively connects each memory cell to a plurality of reading elements.

Abstract translation: 具有控制码的存储器件的解码结构被用于存储器中的存储器，该存储器包括被分组成一页的存储器单元矩阵，每个存储器单元的一个控制信息块相关联，以及多个用于读取多个页面的读取元件 平行。 解码结构将每个读取元件选择性地连接到多个存储单元，并且将每个存储单元选择性地连接到多个读取元件。