Row selection circuit for fast memory devices
    1.
    发明申请
    Row selection circuit for fast memory devices 有权
    用于快速存储器件的行选择电路

    公开(公告)号:US20010024131A1

    公开(公告)日:2001-09-27

    申请号:US09745286

    申请日:2000-12-21

    CPC classification number: G11C8/08 G11C8/10 G11C16/08 G11C16/32

    Abstract: The selection/deselection circuit is for non-volatile memory word lines having a decoding line connected between a supply voltage and ground, and including a series of decoding transistors of the same conductivity controlled by respective selection signals and at least a load transistor whose conductivity is opposite to the conductivity of the decoding transistors in series with the series of transistors and biased by a control voltage. The load transistor produces an activating or deactivating voltage of a memory word line, and a circuit for controlling the load transistor is provided. Such an auxiliary control circuit includes a sensing element in series with the decoding transistors and the load transistor for producing a sensing signal switching between a first value when only one memory line is actually selected and a second value when multiple memory word lines appear to be simultaneously selected. Also, an inverter receives the sensing signal and outputs a first signal. A high pass filter receives the first signal and produces a control transient voltage for transitorily bringing the load transistor to a state of full conduction when the sensing signal switches from the first value to the second value.

    Abstract translation: 选择/取消选择电路是用于具有连接在电源电压和地之间的解码线的非易失性存储字线,并且包括由各个选择信号控制的相同电导率的一系列解码晶体管和至少一个负载晶体管,其导电性为 与与晶体管系列串联的解码晶体管的导电性相反,并由控制电压偏置。 负载晶体管产生存储字线的激活或去激活电压,并且提供用于控制负载晶体管的电路。 这样的辅助控制电路包括与解码晶体管和负载晶体管串联的感测元件,用于当仅实际选择一个存储器线路时产生在第一值之间切换的感测信号,并且当多个存储器字线似乎同时显示时的第二值 选择。 此外,逆变器接收感测信号并输出​​第一信号。 当检测信号从第一值切换到第二值时,高通滤波器接收第一信号并产生控制瞬态电压,用于将负载晶体管暂时地导通到全导通状态。

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