公开(公告)号：US20020140047A1

公开(公告)日：2002-10-03

申请号：US10158424

申请日：2002-05-29

Applicant: STMicroelectronics S.r.I.

Inventor： Paolo Giuseppe Cappelletti ,  Alfonso Maurelli

IPC: H01L021/336 ,  H01L029/00 ,  H01L029/792

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11546 ,  Y10S438/981

Abstract: A process for the manufacturing of an integrated circuit including a low operating voltage, high-performance logic circuitry and an embedded memory device having a high operating voltage higher than the low operating voltage of the logic circuitry, providing for: on first portions of a semiconductor substrate, forming a first gate oxide layer for first transistors operating at the high operating voltage; on second portions of the semiconductor substrate, forming a second gate oxide layer for memory cells of the memory device; on the first and second gate oxide layers, forming from a first polysilicon layer gate electrodes for the first transistors, and floating-gate electrodes for the memory cells; forming over the floating-gate electrodes of the memory cells a dielectric layer; on third portions of the semiconductor substrate, forming a third gate oxide layer for second transistors operating at the low operating voltage; on the dielectric layer and on the third portions of the semiconductor substrate, forming from a second polysilicon layer control gate electrodes for the memory cells, and gate electrodes for the second transistors; in the first portions of the semiconductor substrate, forming source and drain regions for the first transistors; in the second portions of the semiconductor substrate, forming source and drain regions for the memory cells; in the third portions of the semiconductor substrate, forming source and drain regions for the second transistors.

Abstract translation: 一种用于制造集成电路的方法，该集成电路包括低工作电压，高性能逻辑电路和具有高于逻辑电路的低工作电压的高工作电压的嵌入​​式存储器件，其提供：在半导体的第一部分上 衬底，形成用于在高工作电压下工作的第一晶体管的第一栅氧化层; 在所述半导体衬底的第二部分上形成用于所述存储器件的存储器单元的第二栅氧化层; 在第一和第二栅氧化层上形成第一晶体管的第一多晶硅层栅电极和用于存储单元的浮栅电极; 在存储单元的浮栅电极上形成介电层; 在半导体衬底的第三部分上形成用于在低工作电压下工作的第二晶体管的第三栅极氧化层; 在所述电介质层和所述半导体衬底的所述第三部分上，从第二多晶硅层形成用于所述存储单元的控制栅电极和用于所述第二晶体管的栅电极; 在半导体衬底的第一部分中，形成用于第一晶体管的源区和漏区; 在半导体衬底的第二部分中，形成用于存储单元的源区和漏区; 在半导体衬底的第三部分中，形成用于第二晶体管的源区和漏极区。