公开(公告)号：US20020135062A1

公开(公告)日：2002-09-26

申请号：US10153473

申请日：2002-05-21

Applicant: STMicroelectronics S.r.I.

Inventor： Ubaldo Mastromatteo ,  Fabrizio Ghironi ,  Roberto Aina ,  Mauro Bombonati

IPC: H01L023/34

CPC classification number: B81C1/00238 ,  B81C2201/019 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01322

Abstract: An electric connection structure connecting a first silicon body to conductive regions provided on the surface of a second silicon body arranged on the first body. The electric connection structure includes at least one plug region of silicon, which extends through the second body; at least one insulation region laterally surrounding the plug region; and at least one conductive electromechanical connection region arranged between the first body and the second body, and in electrical contact with the plug region and with conductive regions of the first body. To form the plug region, trenches are dug in a first wafer and are filled, at least partially, with insulating material. The plug region is fixed to a metal region provided on a second wafer, by performing a low-temperature heat treatment which causes a chemical reaction between the metal and the silicon. The first wafer is thinned until the trenches and electrical connections are formed on the free face of the first wafer.

Abstract translation: 电连接结构，其将第一硅体与设置在第一体上的第二硅体的表面上的导电区域连接。 电连接结构包括延伸穿过第二主体的硅的至少一个插塞区域; 横向围绕所述插塞区域的至少一个绝缘区域; 以及布置在第一主体和第二主体之间并且与插头区域和第一主体的导电区域电接触的至少一个导电机电连接区域。 为了形成插塞区域，在第一晶片中挖出沟槽，并且至少部分地用绝缘材料填充沟槽。 插塞区域通过进行导致金属与硅之间的化学反应的低温热处理而固定在设置在第二晶片上的金属区域上。 将第一晶片减薄直到沟槽和电连接形成在第一晶片的自由面上。