公开(公告)号：US20020135062A1

公开(公告)日：2002-09-26

申请号：US10153473

申请日：2002-05-21

Applicant: STMicroelectronics S.r.I.

Inventor： Ubaldo Mastromatteo ,  Fabrizio Ghironi ,  Roberto Aina ,  Mauro Bombonati

IPC: H01L023/34

CPC classification number: B81C1/00238 ,  B81C2201/019 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01322

Abstract: An electric connection structure connecting a first silicon body to conductive regions provided on the surface of a second silicon body arranged on the first body. The electric connection structure includes at least one plug region of silicon, which extends through the second body; at least one insulation region laterally surrounding the plug region; and at least one conductive electromechanical connection region arranged between the first body and the second body, and in electrical contact with the plug region and with conductive regions of the first body. To form the plug region, trenches are dug in a first wafer and are filled, at least partially, with insulating material. The plug region is fixed to a metal region provided on a second wafer, by performing a low-temperature heat treatment which causes a chemical reaction between the metal and the silicon. The first wafer is thinned until the trenches and electrical connections are formed on the free face of the first wafer.

Abstract translation: 电连接结构，其将第一硅体与设置在第一体上的第二硅体的表面上的导电区域连接。 电连接结构包括延伸穿过第二主体的硅的至少一个插塞区域; 横向围绕所述插塞区域的至少一个绝缘区域; 以及布置在第一主体和第二主体之间并且与插头区域和第一主体的导电区域电接触的至少一个导电机电连接区域。 为了形成插塞区域，在第一晶片中挖出沟槽，并且至少部分地用绝缘材料填充沟槽。 插塞区域通过进行导致金属与硅之间的化学反应的低温热处理而固定在设置在第二晶片上的金属区域上。 将第一晶片减薄直到沟槽和电连接形成在第一晶片的自由面上。

公开(公告)号：US20040070888A1

公开(公告)日：2004-04-15

申请号：US10601332

申请日：2003-06-20

Applicant: STMicroelectronics S.r.I.

Inventor： Ubaldo Mastromatteo ,  Bruno Murari ,  Paolo Ferrari ,  Simone Sassolini

IPC: G11B005/56

CPC classification number: B81B3/0021 ,  H02N1/006

Abstract: A micro-electro-mechanical device formed by a body of semiconductor material having a thickness and defining a mobile part and a fixed part. The mobile part is formed by a mobile platform, supporting arms extending from the mobile platform to the fixed part, and by mobile electrodes fixed to the mobile platform. The fixed part has fixed electrodes facing the mobile electrodes, a first biasing region fixed to the fixed electrodes, a second biasing region fixed to the supporting arms, and an insulation region of insulating material extending through the entire thickness of the body. The insulation region insulates electrically at least one between the first and the second biasing regions from the rest of the fixed part.

Abstract translation: 由具有厚度并限定可移动部分和固定部分的半导体材料体形成的微电子机械装置。 可移动部分由移动平台，从移动平台延伸到固定部分的支撑臂，以及固定到移动平台的移动电极形成。 固定部分具有面向移动电极的固定电极，固定到固定电极的第一偏置区域，固定到支撑臂的第二偏压区域以及延伸穿过主体整个厚度的绝缘材料的绝缘区域。 绝缘区域在第一和第二偏压区域之间至少一个与固定部件的其余部分绝缘。

公开(公告)号：US20030109183A1

公开(公告)日：2003-06-12

申请号：US10243972

申请日：2002-09-12

Applicant: STMicroelectronics S.r.I. ,  Hewlett-Packard Company

Inventor： Ubaldo Mastromatteo ,  Mauro Bombonati ,  Daniela Morin ,  Marta Mottura ,  Mauro Marchi

IPC: H01R009/22

CPC classification number: B81C1/00269 ,  H01L21/185 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05181 ,  H01L2224/05624 ,  H01L2224/10126 ,  H01L2224/10135 ,  H01L2224/13021 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13124 ,  H01L2224/13164 ,  H01L2224/81136 ,  H01L2224/81139 ,  H01L2224/812 ,  H01L2224/81201 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29099 ,  H01L2924/013

Abstract: A process for bonding two distinct substrates that integrate microsystems, including the steps of forming micro-integrated devices in at least one of two substrates using micro-electronic processing techniques and bonding the substrates. Bonding is performed by forming on a first substrate bonding regions of deformable material and pressing the substrates one against another so as to deform the bonding regions and to cause them to react chemically with the second substrate. The bonding regions are preferably formed by a thick layer of a material chosen from among aluminum, copper and nickel, covered by a thin layer of a material chosen from between palladium and platinum. Spacing regions ensure exact spacing between the two wafers.

公开(公告)号：US20020125582A1

公开(公告)日：2002-09-12

申请号：US10037485

申请日：2001-12-19

Applicant: STMicroelectronics S.r.I.

Inventor： Ubaldo Mastromatteo

IPC: H01L023/48 ,  H01L023/52 ,  H01L029/40

CPC classification number: B81C1/00238 ,  B81C2201/019 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13144 ,  H01L2224/45144 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05684

Abstract: A process for manufacturing an integrated device comprises the steps of: forming, in a first wafer of semiconductor material, integrated structures including semiconductor regions and isolation regions; forming, on a second wafer of semiconductor material, interconnection structures of a metal material including plug elements having at least one bonding region of a metal material capable of reacting with the semiconductor regions of the first wafer; and bonding the first and second wafers together by causing the bonding regions of the plug elements to react directly with the semiconductor regions so as to form a metal silicide. Thereby, the metallurgical operations for forming the interconnection structures are completely independent of the operations required for processing silicon, so that there is no interference whatsoever between the two sets of operations. In addition, the areas where the two wafers are made may be separate, and the interconnection structures may be made with materials incompatible with silicon processing, without any risk of contamination.

Abstract translation: 一种用于制造集成器件的方法包括以下步骤：在半导体材料的第一晶片中形成包括半导体区域和隔离区域的集成结构; 在半导体材料的第二晶片上形成包括具有能够与第一晶片的半导体区域反应的金属材料的至少一个结合区域的插塞元件的金属材料的互连结构; 以及通过使所述插塞元件的接合区域与所述半导体区域直接反应从而形成金属硅化物，将所述第一和第二晶片接合在一起。 因此，用于形成互连结构的冶金操作完全独立于处理硅所需的操作，使得在两组操作之间不存在任何干扰。 此外，制造两个晶片的区域可以是分开的，并且互连结构可以由与硅加工不相容的材料制成，而没有任何污染的风险。

公开(公告)号：US20020123160A1

公开(公告)日：2002-09-05

申请号：US10055029

申请日：2002-01-22

Applicant: STMicroelectronics S.r.I.

Inventor： Ubaldo Mastromatteo

IPC: H01L021/66

CPC classification number: H01L23/5225 ,  H01L23/481 ,  H01L23/60 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/074 ,  H01L29/0657 ,  H01L2223/6622 ,  H01L2224/05599 ,  H01L2224/16145 ,  H01L2224/45099 ,  H01L2224/48463 ,  H01L2224/85399 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

Abstract: The integrated semiconductor device includes a first chip of semiconductor material having first, high-voltage, regions at a first high-value voltage; a second chip of semiconductor material having second high-voltage regions connected to the first voltage; and a third chip of semiconductor material arranged between the first chip and the second chip and having at least one low-voltage region at a second, low-value, voltage. A through connection region is formed in the third chip and is connected to the first and second high-voltage regions; through insulating regions surround the through connection region and insulate it from the low-voltage region.

Abstract translation: 集成半导体器件包括具有第一高电压值的第一高电压区域的半导体材料的第一芯片; 具有连接到第一电压的第二高电压区域的第二半导体材料芯片; 以及布置在所述第一芯片和所述第二芯片之间并且具有第二低电压值的至少一个低电压区域的半导体材料的第三芯片。 在第三芯片中形成贯通连接区域并连接到第一和第二高压区域; 通过绝缘区域围绕通过连接区域并将其与低电压区域绝缘。

公开(公告)号：US20040031973A1

公开(公告)日：2004-02-19

申请号：US10446589

申请日：2003-05-27

Applicant: STMicroelectronics S.r.I

Inventor： Carlo Cognetti ,  Ubaldo Mastromatteo

IPC: H01L027/10

CPC classification number: H01L31/18 ,  H01L31/0203 ,  H01L31/02325 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/11 ,  H01L2224/29011 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2224/83 ,  H01L2224/05099

Abstract: A process for manufacturing encapsulated optical sensors, including the steps of: forming a plurality of mutually spaced optical sensors in a wafer of semiconductor material; bonding a plate of transparent material to the wafer so as to seal the optical sensors; and dividing the wafer into a plurality of dies, each comprising an optical sensor and a respective portion of the plate.

Abstract translation: 一种用于制造封装的光学传感器的方法，包括以下步骤：在半导体材料的晶片中形成多个相互间隔的光学传感器; 将透明材料板粘合到晶片上以便密封光学传感器; 并将晶片分成多个模具，每个模具包括光学传感器和板的相应部分。

公开(公告)号：US20030222354A1

公开(公告)日：2003-12-04

申请号：US10406633

申请日：2003-04-02

Applicant: STMicroelectronics S.r.I.

Inventor： Ubaldo Mastromatteo ,  Paolo Ferrari

IPC: H01L029/00 ,  H01L029/40 ,  H01L021/4763 ,  H01L021/44 ,  H01L023/04 ,  H01L023/48 ,  H01L023/52

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05572 ,  H01L2224/13025 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/1461 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: The process for manufacturing a through insulated interconnection is performed by forming, in a body of semiconductor material, a trench extending from the front (of the body for a thickness portion thereof; filling the trench with dielectric material; thinning the body starting from the rear until the trench, so as to form an insulated region surrounded by dielectric material; and forming a conductive region extending inside said insulated region between the front and the rear of the body and having a higher conductivity than the first body. The conductive region includes a metal region extending in an opening formed inside the insulated region or of a heavily doped semiconductor region, made prior to filling of the trench.

Abstract translation: 通过绝缘互连制造的方法是通过在半导体材料体中形成从前部（其主体的厚度部分）延伸的沟槽;用电介质材料填充沟槽;从后面开始使身体变薄 直到形成由电介质材料包围的绝缘区域，形成在主体前后的绝缘区域内延伸的导电性区域，并具有比第1主体高的导电性，导电区域包括： 金属区域在形成在绝缘区域内的开口中延伸，或者在填充沟槽之前制成的重掺杂半导体区域。

公开(公告)号：US20020041729A1

公开(公告)日：2002-04-11

申请号：US09925847

申请日：2001-08-08

Applicant: STMicroelectronics S.r.I.

Inventor： Ubaldo Mastromatteo ,  Bruno Murari

IPC: G02B006/26 ,  G02B006/35

CPC classification number: H02N1/004 ,  B81B3/0051 ,  B81B2201/045 ,  B81B2203/051 ,  B81B2203/058 ,  F16H21/02 ,  G02B26/0841 ,  G02B26/0866

Abstract: A microelectromechanical structure, usable in an optical switch for directing a light beam towards one of two light guide elements, including: a mirror element, rotatably movable; an actuator, which can translate; and a motion conversion assembly, arranged between the mirror element and the actuator. The motion conversion assembly includes a projection integral with the mirror element and elastic engagement elements integral with the actuator and elastically loaded towards the projection. The elastic engagement elements are formed by metal plates fixed to the actuator at one of their ends and engaging the projection with an abutting edge countershaped with respect to the projection.