公开(公告)号：US20040151023A1

公开(公告)日：2004-08-05

申请号：US10715883

申请日：2003-11-18

Applicant: STMicroelectronics S.r.I. ,  OVONYX Inc.

Inventor： Osama Khouri ,  Ferdinando Bedeschi ,  Claudio Resta

IPC: G11C011/00

CPC classification number: G11C7/04 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/009 ,  G11C2029/5002 ,  G11C2213/79

Abstract: A phase change memory includes a temperature sensor having a resistance variable with temperature with the same law as a phase-change storage element. The temperature sensor is formed by a resistor of chalcogenic material furnishing an electrical quantity that reproduces the relationship between the resistance of a phase change memory cell and temperature; the electrical quantity is processed so as to generate reference quantities as necessary for writing and reading the memory cells. The chalcogenic resistor has the same structure as a memory cell and is programmed with precision, preferably in the reset state.

Abstract translation: 相变存储器包括具有与相变存储元件相同定律的具有温度的电阻变化的温度传感器。 该温度传感器是由一个硫化物材料的电阻器形成的，它提供一个再现相变存储器单元电阻和温度之间的关系的电量; 对电量进行处理，以便产生写入和读取存储单元所需的参考量。 硫属电阻器具有与存储器单元相同的结构，并且精确地编程，优选地处于复位状态。

公开(公告)号：US20030185047A1

公开(公告)日：2003-10-02

申请号：US10319439

申请日：2002-12-12

Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

Inventor： Osama Khouri ,  Ferdinando Bedeschi ,  Giorgio Bosisio ,  Fabio Pellizzer

IPC: G11C011/00

CPC classification number: G11C13/0004 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

Abstract: The phase-change nonvolatile memory array is formed by a plurality of memory cells extending in a first and in a second direction orthogonal to each other. A plurality of column-selection lines extend parallel to the first direction. A plurality of word-selection lines extend parallel to the second direction. Each memory cell includes a PCM storage element and a selection transistor. A first terminal of the selection transistor is connected to a first terminal of the PCM storage element, and the control terminal of the selection transistor is connected to a respective word-selection line. A second terminal of the PCM storage element is connected to a respective column-selection line, and a second terminal of the selection transistor is connected to a reference-potential region while reading and programming the memory cells.

Abstract translation: 相变非易失性存储器阵列由在彼此正交的第一和第二方向上延伸的多个存储单元形成。 多个列选择线平行于第一方向延伸。 多个字选择线平行于第二方向延伸。 每个存储单元包括PCM存储元件和选择晶体管。 选择晶体管的第一端子连接到PCM存储元件的第一端子，并且选择晶体管的控制端子连接到相应的字选择线。 PCM存储元件的第二端子连接到相应的列选择线，并且在读取和编程存储器单元的同时，选择晶体管的第二端子连接到参考电位区域。

公开(公告)号：US20030223285A1

公开(公告)日：2003-12-04

申请号：US10331185

申请日：2002-12-27

Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

Inventor： Osama Khouri ,  Ferdinando Bedeschi

IPC: G11C029/00

CPC classification number: G11C13/0026 ,  G11C7/22 ,  G11C13/0038 ,  G11C16/24 ,  G11C2216/22

Abstract: A nonvolatile memory device is described comprising a memory array, a row decoder and a column selector for addressing the memory cells of the memory array, and a biasing stage for biasing the array access device terminal of the addressed memory cell. The biasing stage is arranged between the column selector and the memory array and comprises a biasing transistor having a drain terminal connected to the column selector, a source terminal connected to the array access device terminal of the addressed memory cell, and a gate terminal receiving a logic driving signal, the logic levels of which are defined by precise and stable voltages and are generated by a logic block and an output buffer cascaded together. The output buffer may be supplied with either a read voltage or a program voltage supplied by a multiplexer. The biasing transistor may be either included as part of the column selector and formed by the selection transistor which is closest to the addressed memory cell or distinct from the selection transistors of the column selector.

Abstract translation: 描述了一种非易失性存储器件，其包括用于寻址存储器阵列的存储单元的存储器阵列，行解码器和列选择器，以及用于偏置寻址的存储器单元的阵列存取器件端子的偏置级。 偏置级布置在列选择器和存储器阵列之间，并且包括偏置晶体管，漏极端子连接到列选择器，源极端子连接到寻址存储单元的阵列存取器件端子，栅极端子接收 逻辑驱动信号，其逻辑电平由精确和稳定的电压定义，并由逻辑块和输出缓冲器一起级联产生。 可以向输出缓冲器提供由多路复用器提供的读取电压或编程电压。 偏置晶体管可以被包括为列选择器的一部分，并且由选择晶体管形成，该选择晶体管最靠近寻址的存储单元或与列选择器的选择晶体管不同。