PHOTONIC IC CHIP
    1.
    发明申请

    公开(公告)号:US20220155519A1

    公开(公告)日:2022-05-19

    申请号:US17649520

    申请日:2022-01-31

    摘要: A photonic integrated circuit chip includes vertical grating couplers defined in a first layer. Second insulating layers overlie the vertical grating coupler and an interconnection structure with metal levels is embedded in the second insulating layers. A cavity extends in depth through the second insulating layers all the way to an intermediate level between the couplers and the metal level closest to the couplers. The cavity has lateral dimensions such that the cavity is capable of receiving a block for holding an array of optical fibers intended to be optically coupled to the couplers.

    Phase modulator device and method

    公开(公告)号:US11947202B2

    公开(公告)日:2024-04-02

    申请号:US18295121

    申请日:2023-04-03

    IPC分类号: G02F1/01 G02B6/12 G02F1/035

    摘要: The present disclosure relates to a method including the following steps: a) forming a waveguide from a first material, the waveguide being configured to guide an optical signal; b) forming a layer made of a second material that is electrically conductive and transparent to a wavelength of the optical signal, steps a) and b) being implemented such that the layer made of the second material is in contact with at least one of the faces of the waveguide, or is separated from the at least one of the faces by a distance of less than half, preferably less than a quarter, of the wavelength of the optical signal. The application further relates to a phase modulator, in particular obtained by such a method.

    METHOD OF MAKING A CAPACITIVE OPTICAL MODULATOR

    公开(公告)号:US20230280630A1

    公开(公告)日:2023-09-07

    申请号:US18317705

    申请日:2023-05-15

    IPC分类号: G02F1/225 G02F1/025 G02F1/035

    摘要: A semiconductor device can be formed by etching a cavity in a first silicon layer that overlies an insulating layer, epitaxially growing a germanium or silicon-germanium layer in the cavity, epitaxially growing a second silicon layer in the cavity, etching the second silicon layer and the germanium or silicon-germanium layer to the floor of the cavity to define a first strip in the second silicon layer and a second strip in the germanium or silicon-germanium layer, selectively etching a portion of the second strip to decrease the width of the second strip, filling cavity portions arranged on either side of the first and second strips with an insulator, depositing an upper insulating layer over the first and second strips, and bonding a layer of III-V material to the upper insulating layer.

    Photonic Devices and Methods of Fabrication Thereof

    公开(公告)号:US20190265518A1

    公开(公告)日:2019-08-29

    申请号:US16254753

    申请日:2019-01-23

    IPC分类号: G02F1/025

    摘要: In one aspect, a photonic device includes a first region having a first doping type, where the first region is divided into an upper portion made of silicon-germanium and a lower portion made of silicon. The device further includes a second region having a second doping type. The first region and the second region contact to form a vertical PN junction.

    CAPACITIVE OPTICAL MODULATOR
    6.
    发明申请

    公开(公告)号:US20220004076A1

    公开(公告)日:2022-01-06

    申请号:US17476668

    申请日:2021-09-16

    IPC分类号: G02F1/225 G02F1/025 G02F1/035

    摘要: A capacitive electro-optical modulator includes a silicon layer having a cavity having sidewalls and a floor. A germanium or silicon-germanium strip overlies the silicon layer within the cavity. A silicon strip overlies the germanium or silicon-germanium strip within the cavity. The silicon strip is wider than the germanium or silicon-germanium strip. An insulator fills the cavity laterally adjacent the germanium or silicon-germanium strip and the silicon strip and extending between the sidewalls of the cavity. An upper insulating layer overlies the silicon strip and the insulator. A layer of III-V material overlies the upper insulating layer. The layer of III-V material formed as a third strip is arranged facing the silicon strip and separated therefrom by a portion of the upper insulating layer.

    Capacitive optical modulator
    7.
    发明授权

    公开(公告)号:US11150533B2

    公开(公告)日:2021-10-19

    申请号:US16931090

    申请日:2020-07-16

    IPC分类号: G02F1/225 G02F1/025 G02F1/035

    摘要: A capacitive electro-optical modulator includes a silicon layer, a germanium or silicon-germanium strip overlying the silicon layer, and a silicon strip overlying the germanium or silicon-germanium strip. The silicon strip is wider than the germanium or silicon-germanium strip. An insulator is laterally adjacent the germanium or silicon-germanium strip and the silicon strip and has an upper surface that is flush with an upper surface of the silicon strip. An insulating layer overlies the insulator and the silicon strip. A layer of III-V material overlies the insulating layer. The layer of III-V material is formed as a third strip arranged facing the silicon strip and separated therefrom by a portion of the insulating layer.

    CAPACITIVE OPTICAL MODULATOR
    8.
    发明申请

    公开(公告)号:US20210018815A1

    公开(公告)日:2021-01-21

    申请号:US16931090

    申请日:2020-07-16

    IPC分类号: G02F1/225 G02F1/025 G02F1/035

    摘要: A capacitive electro-optical modulator includes a silicon layer, a germanium or silicon-germanium strip overlying the silicon layer, and a silicon strip overlying the germanium or silicon-germanium strip. The silicon strip is wider than the germanium or silicon-germanium strip. An insulator is laterally adjacent the germanium or silicon-germanium strip and the silicon strip and has an upper surface that is flush with an upper surface of the silicon strip. An insulating layer overlies the insulator and the silicon strip. A layer of III-V material overlies the insulating layer. The layer of III-V material is formed as a third strip arranged facing the silicon strip and separated therefrom by a portion of the insulating layer.

    Photonic IC chip
    10.
    发明授权

    公开(公告)号:US11269141B2

    公开(公告)日:2022-03-08

    申请号:US16821370

    申请日:2020-03-17

    摘要: A photonic integrated circuit chip includes vertical grating couplers defined in a first layer. Second insulating layers overlie the vertical grating coupler and an interconnection structure with metal levels is embedded in the second insulating layers. A cavity extends in depth through the second insulating layers all the way to an intermediate level between the couplers and the metal level closest to the couplers. The cavity has lateral dimensions such that the cavity is capable of receiving a block for holding an array of optical fibers intended to be optically coupled to the couplers.