公开(公告)号：US20190108886A1

公开(公告)日：2019-04-11

申请号：US16145734

申请日：2018-09-28

Applicant: STMicroelectronics S.r.l.

Inventor： Carmelo Paolino ,  Antonino Conte ,  Anna Rita Maria Lipani

IPC: G11C16/28 ,  G11C7/06 ,  G11C16/24

CPC classification number: G11C16/28 ,  G11C7/065 ,  G11C7/08 ,  G11C13/004 ,  G11C13/0061 ,  G11C16/0408 ,  G11C16/24 ,  G11C2013/0042 ,  G11C2013/0045 ,  G11C2013/0054 ,  G11C2207/063

Abstract: A sense-amplifier circuit can be used with a non-volatile memory device having a memory array with memory cells arranged in word lines and bit lines and coupled to respective source lines. The circuit has a first circuit branch and a second circuit branch, which receive on a respective first comparison input and second comparison input, during a reading step of a datum stored in a memory cell, a cell current from the bit line associated to the memory cell and a reference current, from a reference bit line in a differential reading operation or from a current-reference generator in a single-ended reading operation. The first and second circuit branches generate, during the datum-reading step, a first output voltage and a second output voltage, as a function of the difference between the cell current and the reference current.

公开(公告)号：US10658048B2

公开(公告)日：2020-05-19

申请号：US16104001

申请日：2018-08-16

Applicant: STMicroelectronics S.r.l.

Inventor： Antonino Conte ,  Loredana Chiaramonte ,  Anna Rita Maria Lipani

IPC: G11C16/28 ,  G11C16/24 ,  G11C16/04

Abstract: A sense structure includes: a sense amplifier core configured to compare a measurement current with a reference current; a cascode transistor coupled to the sense amplifier core and configured to be coupled to a load; a switch coupled between a bias voltage node and a control terminal of the cascode transistor; a local capacitor having a first terminal coupled to the control terminal of the cascode transistor; a first transistor coupled between a second terminal of the local capacitor and a reference terminal; and a control circuit coupled to a control terminal of the first transistor, the control circuit configured to disconnect the local capacitor from the reference terminal to produce a voltage overshoot in the control terminal of the cascode transistor, and after disconnecting the local capacitor from the reference terminal, limit or reduce the voltage overshoot by adjusting a voltage of the control terminal of the first transistor.

公开(公告)号：US10593410B2

公开(公告)日：2020-03-17

申请号：US16145734

申请日：2018-09-28

Applicant: STMicroelectronics S.r.l.

Inventor： Carmelo Paolino ,  Antonino Conte ,  Anna Rita Maria Lipani

IPC: G11C16/06 ,  G11C16/28 ,  G11C16/04 ,  G11C16/24 ,  G11C7/06 ,  G11C7/08 ,  G11C13/00

Abstract: A sense-amplifier circuit can be used with a non-volatile memory device having a memory array with memory cells arranged in word lines and bit lines and coupled to respective source lines. The circuit has a first circuit branch and a second circuit branch, which receive on a respective first comparison input and second comparison input, during a reading step of a datum stored in a memory cell, a cell current from the bit line associated to the memory cell and a reference current, from a reference bit line in a differential reading operation or from a current-reference generator in a single-ended reading operation. The first and second circuit branches generate, during the datum-reading step, a first output voltage and a second output voltage, as a function of the difference between the cell current and the reference current.

公开(公告)号：US20200058360A1

公开(公告)日：2020-02-20

申请号：US16104001

申请日：2018-08-16

Applicant: STMicroelectronics S.r.l.

Inventor： Antonino Conte ,  Loredana Chiaramonte ,  Anna Rita Maria Lipani

IPC: G11C16/28 ,  G11C16/04 ,  G11C16/24

Abstract: A sense structure includes: a sense amplifier core configured to compare a measurement current with a reference current; a cascode transistor coupled to the sense amplifier core and configured to be coupled to a load; a switch coupled between a bias voltage node and a control terminal of the cascode transistor; a local capacitor having a first terminal coupled to the control terminal of the cascode transistor; a first transistor coupled between a second terminal of the local capacitor and a reference terminal; and a control circuit coupled to a control terminal of the first transistor, the control circuit configured to disconnect the local capacitor from the reference terminal to produce a voltage overshoot in the control terminal of the cascode transistor, and after disconnecting the local capacitor from the reference terminal, limit or reduce the voltage overshoot by adjusting a voltage of the control terminal of the first transistor.