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公开(公告)号：US20180108405A1
公开(公告)日：2018-04-19
申请号：US15842347
申请日：2017-12-14
Applicant: STMicroelectronics S.r.l.
Inventor： Maurizio Francesco Perroni , Carmelo Paolino , Salvatore Polizzi
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C13/0004 , G11C13/0026 , G11C13/0064 , G11C13/0069 , G11C17/18 , G11C2013/0042
Abstract: A phase change memory device includes two portions with local bitlines connected to memory cells. A reading stage is configured to read logic data stored by the first and second memory cells. A first main bitline extends between the reading stage and the first local bitlines and a first main switch is coupled between the first main bitline and reading stage and likewise for the second portion. Local switches are associated with respective ones of the local bitlines. A first reference signal generator is coupled to the reading stage. The phase change memory device is configured to operate in a first reading mode, in which the logic data stored by the first memory cell is read by the reading stage by comparison with the reference signal.
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公开(公告)号：US09964976B2
公开(公告)日：2018-05-08
申请号：US15596895
申请日：2017-05-16
Applicant: STMicroelectronics S.r.l.
Inventor： Antonino Conte , Carmelo Paolino
Abstract: A voltage-regulator device includes an error-amplifier stage configured to receive a first reference voltage and a feedback voltage, an output amplifier stage coupled to the error-amplifier stage and configured to generate an output voltage related to the first reference voltage by an amplification factor, and a feedback stage configured to generate the feedback voltage. A compensation stage is configured to implement a second feedback loop, and cause, in response to a variation of the output voltage, a corresponding variation of a first biasing voltage for the output amplifier stage. The compensation stage includes a coupling-capacitor element coupled between the output amplifier stage and a first internal node, and a driving module coupled between the first internal node, and the output amplifier stage and configured to generate a compensation voltage for driving the output amplifier stage.
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公开(公告)号：US09684324B2
公开(公告)日：2017-06-20
申请号：US14969103
申请日：2015-12-15
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Antonino Conte , Carmelo Paolino
Abstract: A voltage-regulator device includes an error-amplifier stage configured to receive a first reference voltage and a feedback voltage, an output amplifier stage coupled to the error-amplifier stage and configured to generate an output voltage related to the first reference voltage by an amplification factor, and a feedback stage configured to generate the feedback voltage. A compensation stage is configured to implement a second feedback loop, and cause, in response to a variation of the output voltage, a corresponding variation of a first biasing voltage for the output amplifier stage. The compensation stage includes a coupling-capacitor element coupled between the output amplifier stage and a first internal node, and a driving module coupled between the first internal node, and the output amplifier stage and configured to generate a compensation voltage for driving the output amplifier stage.
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公开(公告)号：US10593410B2
公开(公告)日：2020-03-17
申请号：US16145734
申请日：2018-09-28
Applicant: STMicroelectronics S.r.l.
Inventor： Carmelo Paolino , Antonino Conte , Anna Rita Maria Lipani
Abstract: A sense-amplifier circuit can be used with a non-volatile memory device having a memory array with memory cells arranged in word lines and bit lines and coupled to respective source lines. The circuit has a first circuit branch and a second circuit branch, which receive on a respective first comparison input and second comparison input, during a reading step of a datum stored in a memory cell, a cell current from the bit line associated to the memory cell and a reference current, from a reference bit line in a differential reading operation or from a current-reference generator in a single-ended reading operation. The first and second circuit branches generate, during the datum-reading step, a first output voltage and a second output voltage, as a function of the difference between the cell current and the reference current.
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公开(公告)号：US20180061495A1
公开(公告)日：2018-03-01
申请号：US15476003
申请日：2017-03-31
Applicant: STMicroelectronics S.r.l.
Inventor： Antonino Conte , Carmelo Paolino , Maurizio Francesco Perroni , Salvatore Polizzi
CPC classification number: G11C16/12 , G11C8/08 , G11C13/0004 , G11C16/08 , G11C16/20 , G11C16/26 , H03K3/356113 , H03K19/018521
Abstract: A level shifter circuit is designed to shift an input signal that switches within a first voltage range to supply an output signal that switches within a second voltage range, higher than the first voltage range. A first inverter stage has an input receiving the input signal and also has an output. A first capacitive element is connected between the output of the first input inverter stage and a first holding node. A latch stage is connected between the first holding node and a second holding node that is coupled to an output terminal, on which the output signal is present. The first input inverter stage is designed to operate in the first voltage range, and the latch stage is designed to operate in the second voltage range.
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Patent Agency Ranking
公开(公告)号：US20190108886A1
公开(公告)日：2019-04-11
申请号：US16145734
申请日：2018-09-28
Applicant: STMicroelectronics S.r.l.
Inventor： Carmelo Paolino , Antonino Conte , Anna Rita Maria Lipani
CPC classification number: G11C16/28 , G11C7/065 , G11C7/08 , G11C13/004 , G11C13/0061 , G11C16/0408 , G11C16/24 , G11C2013/0042 , G11C2013/0045 , G11C2013/0054 , G11C2207/063
Abstract: A sense-amplifier circuit can be used with a non-volatile memory device having a memory array with memory cells arranged in word lines and bit lines and coupled to respective source lines. The circuit has a first circuit branch and a second circuit branch, which receive on a respective first comparison input and second comparison input, during a reading step of a datum stored in a memory cell, a cell current from the bit line associated to the memory cell and a reference current, from a reference bit line in a differential reading operation or from a current-reference generator in a single-ended reading operation. The first and second circuit branches generate, during the datum-reading step, a first output voltage and a second output voltage, as a function of the difference between the cell current and the reference current.
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公开(公告)号：US09972394B2
公开(公告)日：2018-05-15
申请号：US15476003
申请日：2017-03-31
Applicant: STMicroelectronics S.r.l.
Inventor： Antonino Conte , Carmelo Paolino , Maurizio Francesco Perroni , Salvatore Polizzi
CPC classification number: G11C16/12 , G11C8/08 , G11C13/0004 , G11C16/08 , G11C16/20 , G11C16/26 , H03K3/356113 , H03K19/018521
Abstract: A level shifter circuit is designed to shift an input signal that switches within a first voltage range to supply an output signal that switches within a second voltage range, higher than the first voltage range. A first inverter stage has an input receiving the input signal and also has an output. A first capacitive element is connected between the output of the first input inverter stage and a first holding node. A latch stage is connected between the first holding node and a second holding node that is coupled to an output terminal, on which the output signal is present. The first input inverter stage is designed to operate in the first voltage range, and the latch stage is designed to operate in the second voltage range.
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公开(公告)号：US09865346B1
公开(公告)日：2018-01-09
申请号：US15475609
申请日：2017-03-31
Applicant: STMicroelectronics S.r.l.
Inventor： Maurizio Francesco Perroni , Carmelo Paolino , Salvatore Polizzi
CPC classification number: G11C13/004 , G11C13/0004 , G11C13/0026 , G11C13/0064 , G11C13/0069 , G11C17/18 , G11C2013/0042
Abstract: A phase change memory device includes two portions with local bitlines connected to memory cells. A reading stage is configured to read logic data stored by the first and second memory cells. A first main bitline extends between the reading stage and the first local bitlines and a first main switch is coupled between the first main bitline and reading stage and likewise for the second portion. Local switches are associated with respective ones of the local bitlines. A first reference signal generator is coupled to the reading stage. The phase change memory device is configured to operate in a first reading mode, in which the logic data stored by the first memory cell is read by the reading stage by comparison with the reference signal.
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公开(公告)号：US10186317B2
公开(公告)日：2019-01-22
申请号：US15842347
申请日：2017-12-14
Applicant: STMicroelectronics S.r.l.
Inventor： Maurizio Francesco Perroni , Carmelo Paolino , Salvatore Polizzi
Abstract: A phase change memory device includes two portions with local bitlines connected to memory cells. A reading stage is configured to read logic data stored by the first and second memory cells. A first main bitline extends between the reading stage and the first local bitlines and a first main switch is coupled between the first main bitline and reading stage and likewise for the second portion. Local switches are associated with respective ones of the local bitlines. A first reference signal generator is coupled to the reading stage. The phase change memory device is configured to operate in a first reading mode, in which the logic data stored by the first memory cell is read by the reading stage by comparison with the reference signal.
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10.发明申请公开(公告)号：US20170248981A1
公开(公告)日：2017-08-31
申请号：US15596895
申请日：2017-05-16
Applicant: STMicroelectronics S.r.l.
Inventor： Antonino Conte , Carmelo Paolino
Abstract: A voltage-regulator device includes an error-amplifier stage configured to receive a first reference voltage and a feedback voltage, an output amplifier stage coupled to the error-amplifier stage and configured to generate an output voltage related to the first reference voltage by an amplification factor, and a feedback stage configured to generate the feedback voltage. A compensation stage is configured to implement a second feedback loop, and cause, in response to a variation of the output voltage, a corresponding variation of a first biasing voltage for the output amplifier stage. The compensation stage includes a coupling-capacitor element coupled between the output amplifier stage and a first internal node, and a driving module coupled between the first internal node, and the output amplifier stage and configured to generate a compensation voltage for driving the output amplifier stage.
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