公开(公告)号：US20220173018A1

公开(公告)日：2022-06-02

申请号：US17674697

申请日：2022-02-17

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Cristina SOMMA

IPC: H01L23/495 ,  H01L23/498

Abstract: One or more embodiments are directed to semiconductor packages and methods in which one or more electrical components are positioned between a semiconductor die and a surface of a substrate. In one embodiment, a semiconductor package includes a substrate having a first surface. One or more electrical components are electrically coupled to electrical contacts on the first surface of the substrate. A semiconductor die is positioned on the one or more electrical components, and the semiconductor die has an active surface that faces away from the substrate. An adhesive layer is on the first surface of the substrate and on the one or more electrical components, and the semiconductor die is spaced apart from the one or more electrical components by the adhesive layer. Wire bonds are provided that electrically couples the active surface of the semiconductor die to the substrate.

公开(公告)号：US20240096759A1

公开(公告)日：2024-03-21

申请号：US18508007

申请日：2023-11-13

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Cristina SOMMA ,  Fulvio Vittorio FONTANA

IPC: H01L23/495

CPC classification number: H01L23/49503 ,  H01L23/49517 ,  H01L23/49575

Abstract: One or more embodiments are directed to quad flat no-lead (QFN) semiconductor packages, devices, and methods in which one or more electrical components are positioned between a die pad of a QFN leadframe and a semiconductor die. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and at least one electrical component that has a first contact on the die pad and a second contact on the lead. A semiconductor die is positioned on the at least one electrical component and is spaced apart from the die pad by the at least one electrical component. The device further includes at least one conductive wire, or wire bond, that electrically couples the at least one lead to the semiconductor die.

公开(公告)号：US20200176363A1

公开(公告)日：2020-06-04

申请号：US16782797

申请日：2020-02-05

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Cristina SOMMA ,  Fulvio Vittorio FONTANA

IPC: H01L23/495

Abstract: One or more embodiments are directed to quad flat no-lead (QFN) semiconductor packages, devices, and methods in which one or more electrical components are positioned between a die pad of a QFN leadframe and a semiconductor die. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and at least one electrical component that has a first contact on the die pad and a second contact on the lead. A semiconductor die is positioned on the at least one electrical component and is spaced apart from the die pad by the at least one electrical component. The device further includes at least one conductive wire, or wire bond, that electrically couples the at least one lead to the semiconductor die.

公开(公告)号：US20240145364A1

公开(公告)日：2024-05-02

申请号：US18386069

申请日：2023-11-01

Applicant: STMicroelectronics S.r.l.

Inventor： Aurora SANNA ,  Cristina SOMMA ,  Damian HALICKI

IPC: H01L23/498 ,  H01L23/48 ,  H01L23/528

CPC classification number: H01L23/49816 ,  H01L23/481 ,  H01L23/49838 ,  H01L23/5286

Abstract: A BGA package includes an array of electrically conductive balls providing electrical contact for a semiconductor die. A power channel is provided to convey power supply current towards the semiconductor die. The power channel is formed by a stack of electrically conductive planes. The electrically conductive planes are stacked in a stepped arrangement wherein a number of stacked planes in each step of the stack increases in a direction from a distal end to a proximal end of the power channel. Adjacent electrically conductive planes in the stack of the power channel are electrically coupled with electrically conductive vias extending therebetween. Current conduction paths towards the die area thus have resistance values that decrease from the distal end to the proximal end of the power channel.

公开(公告)号：US20200219799A1

公开(公告)日：2020-07-09

申请号：US16824429

申请日：2020-03-19

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Cristina SOMMA

IPC: H01L23/495 ,  H01L23/498

Abstract: One or more embodiments are directed to semiconductor packages and methods in which one or more electrical components are positioned between a semiconductor die and a surface of a substrate. In one embodiment, a semiconductor package includes a substrate having a first surface. One or more electrical components are electrically coupled to electrical contacts on the first surface of the substrate. A semiconductor die is positioned on the one or more electrical components, and the semiconductor die has an active surface that faces away from the substrate. An adhesive layer is on the first surface of the substrate and on the one or more electrical components, and the semiconductor die is spaced apart from the one or more electrical components by the adhesive layer. Wire bonds are provided that electrically couples the active surface of the semiconductor die to the substrate.

公开(公告)号：US20190287880A1

公开(公告)日：2019-09-19

申请号：US15925420

申请日：2018-03-19

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Cristina SOMMA ,  Fulvio Vittorio FONTANA

IPC: H01L23/495

Abstract: One or more embodiments are directed to quad flat no-lead (QFN) semiconductor packages, devices, and methods in which one or more electrical components are positioned between a die pad of a QFN leadframe and a semiconductor die. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and at least one electrical component that has a first contact on the die pad and a second contact on the lead. A semiconductor die is positioned on the at least one electrical component and is spaced apart from the die pad by the at least one electrical component. The device further includes at least one conductive wire, or wire bond, that electrically couples the at least one lead to the semiconductor die.

公开(公告)号：US20220173064A1

公开(公告)日：2022-06-02

申请号：US17537112

申请日：2021-11-29

Applicant: STMicroelectronics S.r.l.

Inventor： Cristina SOMMA ,  Aurora SANNA ,  Damian HALICKI

IPC: H01L23/00 ,  H01L23/498

Abstract: A semiconductor die is mounted at a die area of a ball grid array package that includes an array of electrically-conductive ball. A power channel conveys a power supply current to the semiconductor die. The power channel is formed by an electrically-conductive connection plane layers extending in a longitudinal direction between a distal end at a periphery of the package and a proximal end at the die area. A distribution of said electrically-conductive balls is made along the longitudinal direction. The electrically-conductive connection plane layer includes subsequent portions in the longitudinal direction between adjacent electrically-conductive balls of the distribution. Respective electrical resistance values of the subsequent portions monotonously decrease from the distal end to the proximal end. A uniform distribution of power supply current over the length of the power channel is thus facilitated.

公开(公告)号：US20210249337A1

公开(公告)日：2021-08-12

申请号：US17244378

申请日：2021-04-29

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Cristina SOMMA ,  Fulvio Vittorio FONTANA

IPC: H01L23/495

Abstract: One or more embodiments are directed to quad flat no-lead (QFN) semiconductor packages, devices, and methods in which one or more electrical components are positioned between a die pad of a QFN leadframe and a semiconductor die. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and at least one electrical component that has a first contact on the die pad and a second contact on the lead. A semiconductor die is positioned on the at least one electrical component and is spaced apart from the die pad by the at least one electrical component. The device further includes at least one conductive wire, or wire bond, that electrically couples the at least one lead to the semiconductor die.

公开(公告)号：US20210167029A1

公开(公告)日：2021-06-03

申请号：US17108694

申请日：2020-12-01

Applicant: STMicroelectronics S.r.l.

Inventor： Cristina SOMMA ,  Giovanni GRAZIOSI

IPC: H01L23/00 ,  H01L27/02 ,  H01L23/13 ,  H01L23/14

Abstract: A first device includes a rectangular substrate having a first width and a first length and a first pattern of electrical interface nodes at first, second and third sides with a first set of electrical interface nodes at the fourth side. A second device includes a second rectangular substrate having a second width equal to the first width, a second length and a median line extending in the direction of the second width. A second pattern of electrical interface nodes for the second device includes two unmorphed replicas of the first pattern arranged mutually rotated 180° on opposite sides of the median line as well as two second sets of electrical interface nodes formed by two smaller morphed replicas of the first set of electrical interface nodes arranged mutually rotated 180° on opposite sides of said median line.

公开(公告)号：US20190287881A1

公开(公告)日：2019-09-19

申请号：US15925477

申请日：2018-03-19

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Cristina SOMMA

IPC: H01L23/495 ,  H01L23/498

Abstract: One or more embodiments are directed to semiconductor packages and methods in which one or more electrical components are positioned between a semiconductor die and a surface of a substrate. In one embodiment, a semiconductor package includes a substrate having a first surface. One or more electrical components are electrically coupled to electrical contacts on the first surface of the substrate. A semiconductor die is positioned on the one or more electrical components, and the semiconductor die has an active surface that faces away from the substrate. An adhesive layer is on the first surface of the substrate and on the one or more electrical components, and the semiconductor die is spaced apart from the one or more electrical components by the adhesive layer. Wire bonds are provided that electrically couples the active surface of the semiconductor die to the substrate.