公开(公告)号：US20180240519A1

公开(公告)日：2018-08-23

申请号：US15797732

申请日：2017-10-30

Applicant: STMicroelectronics S.r.l.

Inventor： Davide Manfre ,  Cesare Torti ,  Fabio Enrico Carlo Disegni

IPC: G11C13/00

CPC classification number: G11C13/0038 ,  G11C8/16 ,  G11C13/0004 ,  G11C13/0023

Abstract: An embodiment memory device includes a memory array having a plurality of bit lines, a low-voltage connection path configured to connect, in an operational phase of the device, an access terminal to a selected local bit line of the plurality of bit lines, and a high-voltage connection path configured to connect, in the operational phase of the device, the access terminal to the selected local bit line, in parallel with the low-voltage connection path.

公开(公告)号：US10255973B2

公开(公告)日：2019-04-09

申请号：US15797732

申请日：2017-10-30

Applicant: STMicroelectronics S.r.l.

Inventor： Davide Manfre ,  Cesare Torti ,  Fabio Enrico Carlo Disegni

IPC: G11C13/00 ,  G11C8/16

Abstract: An embodiment memory device includes a memory array having a plurality of bit lines, a low-voltage connection path configured to connect, in an operational phase of the device, an access terminal to a selected local bit line of the plurality of bit lines, and a high-voltage connection path configured to connect, in the operational phase of the device, the access terminal to the selected local bit line, in parallel with the low-voltage connection path.