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公开(公告)号：US11355191B2
公开(公告)日：2022-06-07
申请号：US17072887
申请日：2020-10-16
Applicant: STMicroelectronics S.r.l.
Inventor： Fabio Enrico Carlo Disegni , Maurizio Francesco Perroni , Cesare Torti
Abstract: An embodiment method for programming a differential type phase-change memory device comprises, in a first time interval, programming a direct memory cell or the respective complementary one pertaining to a first programming driver by means of a current between SET and RESET; and, in the same first time interval, simultaneously programming a direct memory cell or the respective complementary one pertaining to a second programming driver by means of the same current between SET and RESET. The method further comprises, in a second time interval, programming the other direct memory cell or the respective complementary one pertaining to the first programming driver by means of the other current between SET and RESET; and, in the same second time interval, simultaneously programming the other direct memory cell or the respective complementary one pertaining to the second programming driver by means of the same other current between SET and RESET.
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2.发明申请公开(公告)号：US20190214079A1
公开(公告)日：2019-07-11
申请号：US16227438
申请日：2018-12-20
Applicant: STMicroelectronics S.r.l.
Inventor： Fabio Enrico Carlo Disegni , Cesare Torti , Davide Manfré
Abstract: A memory device including a first memory sector and a second memory sector, each of which includes a respective plurality of local bit lines, which may be selectively coupled to a plurality of main bit lines. The memory device further includes a first amplifier and a second amplifier, and a routing circuit, arranged between the main bit lines and the first and second amplifiers. The routing circuit includes: a first lower switch, arranged between a first lower main bit line and a first input of the first amplifier; a second lower switch, arranged between the first lower main bit line and a first input of the second amplifier; a first upper switch, arranged between a first upper main bit line and the first input of the first amplifier; and a second upper switch, arranged between the first upper main bit line and the first input of the second amplifier. The second inputs of the first and second amplifiers are coupled to a second lower main bit line and to a second upper main bit line, respectively.
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公开(公告)号：US20190043574A1
公开(公告)日：2019-02-07
申请号：US16155659
申请日：2018-10-09
Applicant: STMicroelectronics S.r.l.
Inventor： Cesare Torti , Fabio Enrico Carlo Disegni , Davide Manfré , Massimo Fidone
Abstract: A memory device includes an array of phase-change memory cells and a word line. The memory device includes a control circuit, a first pull-up MOSFET and a second pull-up MOSFET connected in series between a first power-supply node set at a first supply voltage and the word line, a first pull-down MOSFET and a second pull-down MOSFET connected in series between the word line and a second power-supply node set at a reference potential, and a biasing MOSFET connected between the word line and a third power-supply node set at a second supply voltage higher than the first supply voltage. The first and second pull-up MOSFETs and the first and second pull-down MOSFETs have breakdown voltages lower than the breakdown voltage of the biasing MOSFET.
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公开(公告)号：US11475960B2
公开(公告)日：2022-10-18
申请号：US17306266
申请日：2021-05-03
Inventor： Fabio Enrico Carlo Disegni , Laura Capecchi , Marcella Carissimi , Vikas Rana , Cesare Torti
Abstract: An embodiment non-volatile memory device includes an array of memory cells in rows and columns; a plurality of local bitlines, the memory cells of each column being coupled to a corresponding local bitline; a plurality of main bitlines, each main bitline being coupleable to a corresponding subset of local bitlines; a plurality of program driver circuits, each having a corresponding output node and injecting a programming current in the corresponding output node, each output node coupleable to a corresponding subset of main bitlines. Each program driver circuit further includes a corresponding limiter circuit that is electrically coupled, for each main bitline of the corresponding subset, to a corresponding sense node whose voltage depends, during writing, on the voltage on the corresponding main bitline. Each limiter circuit turns off the corresponding programming current, in case the voltage on any of the corresponding sense nodes overcomes a reference voltage.
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公开(公告)号：US20210183442A1
公开(公告)日：2021-06-17
申请号：US17123518
申请日：2020-12-16
Applicant: STMicroelectronics S.r.l.
IPC: G11C13/00
Abstract: An embodiment non-volatile memory device includes an array of memory cells, coupled to word lines, and a row decoder including a pull-down stage and a pull-up stage, which includes, for each word line: a corresponding control circuit, which generates a corresponding control signal; and a corresponding pull-up switch circuit, which is controlled via the control signal so as to couple/decouple the word line to/from the supply. The control circuit includes: a current mirror, which injects a current into an internal node; and a series circuit, which couples/decouples the corresponding internal node to/from ground, on the basis of selection/deselection of the corresponding word line so as to cause a decrease/increase in a voltage on the corresponding internal node. Each control signal is a function of the voltage on the corresponding internal node.
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Patent Agency Ranking
公开(公告)号：US20210125668A1
公开(公告)日：2021-04-29
申请号：US17072887
申请日：2020-10-16
Applicant: STMicroelectronics S.r.l.
Inventor： Fabio Enrico Carlo Disegni , Maurizio Francesco Perroni , Cesare Torti
IPC: G11C13/00
Abstract: An embodiment method for programming a differential type phase-change memory device comprises, in a first time interval, programming a direct memory cell or the respective complementary one pertaining to a first programming driver by means of a current between SET and RESET; and, in the same first time interval, simultaneously programming a direct memory cell or the respective complementary one pertaining to a second programming driver by means of the same current between SET and RESET. The method further comprises, in a second time interval, programming the other direct memory cell or the respective complementary one pertaining to the first programming driver by means of the other current between SET and RESET; and, in the same second time interval, simultaneously programming the other direct memory cell or the respective complementary one pertaining to the second programming driver by means of the same other current between SET and RESET.
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公开(公告)号：US10522220B2
公开(公告)日：2019-12-31
申请号：US16056818
申请日：2018-08-07
Applicant: STMicroelectronics S.r.l.
Inventor： Fabio Enrico Carlo Disegni , Cesare Torti , Davide Manfre′
Abstract: According to one embodiment, a PCM memory device includes a memory matrix having memory cells of the phase-change type organized in a plurality of word lines and bit lines. Each memory cell has a storage element and an access element including at least one MOS transistor, which is controlled to allow access to the storage element and to carry out read/programming storage operations, in which source terminals of the MOS transistors of access elements of the memory cells of the same word line are connected to the same source line. The source lines of the memory matrix are electrically short-circuited in groups. A single source line driver element for each group of source lines is configured in such a manner as to generate a respective source line driver signal in order to bias in a corresponding manner all the source lines of the respective group.
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公开(公告)号：US20190051348A1
公开(公告)日：2019-02-14
申请号：US16056818
申请日：2018-08-07
Applicant: STMicroelectronics S.r.l.
Inventor： Fabio Enrico Carlo Disegni , Cesare Torti , Davide Manfre'
IPC: G11C13/00
Abstract: According to one embodiment, a PCM memory device includes a memory matrix having memory cells of the phase-change type organized in a plurality of word lines and bit lines. Each memory cell has a storage element and an access element including at least one MOS transistor, which is controlled to allow access to the storage element and to carry out read/programming storage operations, in which source terminals of the MOS transistors of access elements of the memory cells of the same word line are connected to the same source line. The source lines of the memory matrix are electrically short-circuited in groups. A single source line driver element for each group of source lines is configured in such a manner as to generate a respective source line driver signal in order to bias in a corresponding manner all the source lines of the respective group.
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公开(公告)号：US10115460B2
公开(公告)日：2018-10-30
申请号：US15639540
申请日：2017-06-30
Applicant: STMicroelectronics S.r.l.
Inventor： Cesare Torti , Fabio Enrico Carlo Disegni , Davide Manfre′ , Massimo Fidone
Abstract: A memory device includes an array of phase-change memory cells and a word line. The memory device includes a control circuit, a first pull-up MOSFET and a second pull-up MOSFET connected in series between a first power-supply node set at a first supply voltage and the word line, a first pull-down MOSFET and a second pull-down MOSFET connected in series between the word line and a second power-supply node set at a reference potential, and a biasing MOSFET connected between the word line and a third power-supply node set at a second supply voltage higher than the first supply voltage. The first and second pull-up MOSFETs and the first and second pull-down MOSFETs have breakdown voltages lower than the breakdown voltage of the biasing MOSFET.
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10.发明授权公开(公告)号：US11380380B2
公开(公告)日：2022-07-05
申请号：US17088060
申请日：2020-11-03
Applicant: STMicroelectronics S.r.l.
Inventor： Fabio Enrico Carlo Disegni , Maurizio Francesco Perroni , Cesare Torti , Guiseppe Scardino
Abstract: A non-volatile memory device including an array of memory cells coupled to word lines and a row decoder, which includes a first and a second pull-down stage, which are arranged on opposite sides of the array, and include, respectively, for each word line, a corresponding first pull-down switching circuit and a corresponding second pull-down switching circuit, which are coupled to a first point and a second point, respectively, of the first word line. The row decoder moreover comprises a pull-up stage, which includes, for each word line, a corresponding pull-up switching circuit, which can be electronically controlled in order to: couple the first point to a supply node in the step of deselection of the word line; and decouple the first point from the supply node in the step of selection of the word line.
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