公开(公告)号：US20130095624A1

公开(公告)日：2013-04-18

申请号：US13706312

申请日：2012-12-05

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Mario Giuseppe SAGGIO ,  Edoardo ZANETTI ,  Ferruccio FRISINA

IPC: H01L29/66

CPC classification number: H01L29/7811 ,  H01L21/0485 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/66666 ,  H01L29/7802

Abstract: An embodiment of a process for manufacturing an electronic device on a semiconductor body of a material with wide forbidden bandgap having a first conductivity type. The process comprises the steps of: forming, on the semiconductor body, a first mask having a first window and a second window above a first surface portion and a second surface portion of the semiconductor body; forming, within the first and second surface portions of the semiconductor body underneath the first and second windows, at least one first conductive region and one second conductive region having a second conductivity type, the first conductive region and the second conductive region facing one another; forming a second mask on the semiconductor body, the second mask having a plurality of windows above surface portions of the first conductive region and the second conductive region; forming, within the first conductive region and the second conductive region and underneath the plurality of windows, a plurality of third conductive regions having the first conductivity type; removing completely the first and second masks; performing an activation thermal process of the first, second, and third conductive regions at a high temperature; and forming body and source regions.

Abstract translation: 一种用于制造具有第一导电类型的具有宽禁带隙的材料的半导体本体上的电子器件的方法的实施例。 该方法包括以下步骤：在半导体本体上形成第一掩模，该第一掩模在半导体本体的第一表面部分和第二表面部分之上具有第一窗口和第二窗口; 在第一和第二窗口下面的半导体本体的第一和第二表面部分内形成具有第二导电类型的至少一个第一导电区域和一个第二导电区域，第一导电区域和第二导电区域彼此面对; 在所述半导体主体上形成第二掩模，所述第二掩模在所述第一导电区域和所述第二导电区域的表面部分上方具有多个窗口; 在所述第一导电区域和所述第二导电区域内以及所述多个窗口下方形成具有所述第一导电类型的多个第三导电区域; 彻底清除第一和第二个面罩; 在高温下进行第一，第二和第三导电区域的激活热处理; 并形成体和源区。

公开(公告)号：US20140141603A1

公开(公告)日：2014-05-22

申请号：US14166522

申请日：2014-01-28

Applicant: STMicroelectronics S.r.l.

Inventor： Ferruccio FRISINA ,  Mario Giuseppe SAGGIO ,  Angelo MAGRI'

IPC: H01L21/02 ,  H01L21/265

CPC classification number: H01L29/7806 ,  H01L21/02573 ,  H01L21/046 ,  H01L21/265 ,  H01L29/0619 ,  H01L29/0821 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66068 ,  H01L29/732 ,  H01L29/7371 ,  H01L29/7802 ,  H01L29/7804 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/872

Abstract: An embodiment of a vertical-conduction integrated electronic device formed in a body of semiconductor material which includes: a substrate made of a first semiconductor material and with a first type of conductivity, the first semiconductor material having a first bandgap; an epitaxial region made of the first semiconductor material and with the first type of conductivity, which overlies the substrate and defines a first surface; and a first epitaxial layer made of a second semiconductor material, which overlies the first surface and is in direct contact with the epitaxial region, the second semiconductor material having a second bandgap narrower than the first bandgap. The body moreover includes a deep region of a second type of conductivity, extending underneath the first surface and within the epitaxial region.

Abstract translation: 形成在半导体材料体内的垂直导电集成电子器件的实施例包括：由第一半导体材料制成并具有第一导电类型的衬底，第一半导体材料具有第一带隙; 由第一半导体材料制成并且具有第一类型的导电性的外延区域，其覆盖在衬底上并限定第一表面; 以及由第二半导体材料制成的第一外延层，其覆盖在第一表面上并与外延区直接接触，第二半导体材料具有比第一带隙窄的第二带隙。 身体还包括延伸在第一表面下方和外延区域内的第二类导电性的深区域。