公开(公告)号：US11789078B2

公开(公告)日：2023-10-17

申请号：US17714515

申请日：2022-04-06

Applicant: STMicroelectronics S.r.l.

Inventor： Filippo Minnella

IPC: G01R31/3185

CPC classification number: G01R31/318555 ,  G01R31/318572

Abstract: An electronic device includes a processing unit with a memory, a JTAG interface with test-data-input and test-mode-select lines coupled to the processing unit, a bridge circuit, and a multiplexer circuit. The bridge circuit includes a serial communication interface receiving a serial data input signal which conveys an input serial data frame. The bridge circuit includes a serial-to-parallel converter circuit block receiving the input serial data frame, processing the input serial data frame to read first and second subsets of input binary values therefrom, and transmitting the first subset via a first output signal and the second subset via a second output signal. The multiplexer circuit selectively propagates a received test-data-input signal or the first output signal to the test data input line, and selectively propagates a test-mode-select signal or the second output signal to the test mode select line of the JTAG interface.

公开(公告)号：US12056074B2

公开(公告)日：2024-08-06

申请号：US18116912

申请日：2023-03-03

Applicant: STMicroelectronics S.r.l.

Inventor： Filippo Minnella ,  Gea Donzelli

IPC: G06F13/38 ,  G06F13/42 ,  H04L25/02

CPC classification number: G06F13/385 ,  G06F13/4291 ,  H04L25/0262

Abstract: A UART communication interface manages transmission/reception at a baud rate using a baud-rate detection circuit. An edge detector detects edges in a reception signal and resets a count value in a digital counter circuit indicating a time between two consecutive edges. In the absence of a detected edge, the digital counter circuit increases the count value. At a newly detected edge, a validation circuit verifies the count value by asserting a second control signal when the count value is smaller than a maximum, and otherwise de-asserting the second control signal. A register provides a threshold signal by storing the count value when the second control signal is asserted. The threshold signal stored by the register is updated when the time is in a permitted range corresponding to the duration of a single bit. The baud rate may be determined as a function of the threshold signal.

公开(公告)号：US12021454B2

公开(公告)日：2024-06-25

申请号：US17730878

申请日：2022-04-27

Applicant: STMicroelectronics S.r.l.

Inventor： Gerardo Castellano ,  Leonardo Pedone ,  Filippo Minnella ,  Marcello Raimondi

IPC: H02M3/158 ,  H02M1/00 ,  H02M1/08

CPC classification number: H02M3/1586 ,  H02M1/0009 ,  H02M1/08 ,  H02M1/0043

Abstract: A control circuit for a multiphase buck converter includes a regulator circuit and a plurality of phase control circuits. The regulator circuit generates a regulation signal based on a feedback signal and a reference signal, and each phase control circuit receives a current sense signal and generates a respective PWM signal based on the respective current sense signal and the regulation signal. The control circuit includes a first selector circuit and a second selector circuit configured to receive a selection signal and selectively connect each phase control circuit of a subset of the phase control circuits to a PWM signal for driving a respective stage of the multiphase buck converter, and to a current sense signal provided by the respective stage of the multiphase buck converter. A selection control circuit generates the selection signal in order to connect the phase control circuits to different stages of the multiphase buck converter.