公开(公告)号：US12164000B2

公开(公告)日：2024-12-10

申请号：US17460657

申请日：2021-08-30

Applicant: STMicroelectronics S.r.l.

Inventor： Alessandro Cannone ,  Enrico Ferrara ,  Nicola Errico ,  Gea Donzelli

IPC: G01R31/3167 ,  G01R31/28 ,  G01R31/317

Abstract: Disclosed herein is a single integrated circuit chip including main logic that operates a vehicle component such as a valve driver. Isolated from the main logic within the chip is a safety area that operates to verify proper operation of the main logic. A checker circuit within the chip outside of the safety area serves to verify proper operation of the checker circuit. The checker circuit receives signals from the safety circuit and uses combinatorial logic circuit to verify from those signals that the check circuit is operating properly.

公开(公告)号：US20220149859A1

公开(公告)日：2022-05-12

申请号：US17501112

申请日：2021-10-14

Applicant: STMicroelectronics S.r.l.

Inventor： Nicola Errico ,  Marzia Annovazzi ,  Alessandro Cannone ,  Enrico Ferrara ,  Gea Donzelli ,  Paolo Turbanti

IPC: H03M1/10 ,  H03M1/06

Abstract: In an embodiment, a circuit includes N sensing channels. Each channel includes a first main sensing node and a second redundancy sensing node paired therewith. N analog-to-digital converters (ADCs) are coupled to the first sensing nodes, with digital processing circuits coupled to the N ADCs. A pair of multiplexers are coupled to the second sensing nodes and to the N ADCs with a further ADC coupled to the output of the second multiplexer. An error checking circuit is coupled to the outputs of the second multiplexer and the further ADC to compare, at each time window in a sequence of N time windows, a first digital value and a second digital value resulting from conversion to digital of: an analog sensing signal at one of the first sensing nodes, and an analog sensing signal at the second sensing node paired with the selected one of the first sensing nodes.

公开(公告)号：US12056074B2

公开(公告)日：2024-08-06

申请号：US18116912

申请日：2023-03-03

Applicant: STMicroelectronics S.r.l.

Inventor： Filippo Minnella ,  Gea Donzelli

IPC: G06F13/38 ,  G06F13/42 ,  H04L25/02

CPC classification number: G06F13/385 ,  G06F13/4291 ,  H04L25/0262

Abstract: A UART communication interface manages transmission/reception at a baud rate using a baud-rate detection circuit. An edge detector detects edges in a reception signal and resets a count value in a digital counter circuit indicating a time between two consecutive edges. In the absence of a detected edge, the digital counter circuit increases the count value. At a newly detected edge, a validation circuit verifies the count value by asserting a second control signal when the count value is smaller than a maximum, and otherwise de-asserting the second control signal. A register provides a threshold signal by storing the count value when the second control signal is asserted. The threshold signal stored by the register is updated when the time is in a permitted range corresponding to the duration of a single bit. The baud rate may be determined as a function of the threshold signal.

公开(公告)号：US11658674B2

公开(公告)日：2023-05-23

申请号：US17501112

申请日：2021-10-14

Applicant: STMicroelectronics S.r.l.

Inventor： Nicola Errico ,  Marzia Annovazzi ,  Alessandro Cannone ,  Enrico Ferrara ,  Gea Donzelli ,  Paolo Turbanti

IPC: H03M1/10 ,  H03M1/06

CPC classification number: H03M1/1071 ,  H03M1/0687

Abstract: In an embodiment, a circuit includes N sensing channels. Each channel includes a first main sensing node and a second redundancy sensing node paired therewith. N analog-to-digital converters (ADCs) are coupled to the first sensing nodes, with digital processing circuits coupled to the N ADCs. A pair of multiplexers are coupled to the second sensing nodes and to the N ADCs with a further ADC coupled to the output of the second multiplexer. An error checking circuit is coupled to the outputs of the second multiplexer and the further ADC to compare, at each time window in a sequence of N time windows, a first digital value and a second digital value resulting from conversion to digital of: an analog sensing signal at one of the first sensing nodes, and an analog sensing signal at the second sensing node paired with the selected one of the first sensing nodes.