-
公开(公告)号：US09646713B2
公开(公告)日：2017-05-09
申请号：US15140023
申请日：2016-04-27
IPC分类号： G11C17/18
CPC分类号： G11C17/18 , G11C11/4125 , G11C17/16 , H03K3/02335 , H03K19/00338 , H03K19/17764
摘要： A radiation hardened memory cell includes an odd number of storage elements configured to redundantly store an input data logic signal. The storage elements include output lines for outputting respective logic signals having respective logic values. A logic combination network receives the respective logic signals and is configured to generate an output signal having a same logic value as a majority of the logic signals output from the storage elements. An exclusive logic sum circuit receives the respective logic signals output from the storage elements and is configured to produce a refresh of the logic data signal as stored in the storage elements when one of the logic signals output from the storage elements undergoes a logic value transition due to an error event.
-
公开(公告)号：US20180159317A1
公开(公告)日：2018-06-07
申请号：US15596465
申请日：2017-05-16
摘要： A power transistor supplying power to a load is coupled to a current limiter circuit including a differential amplifier that operates to detect a difference between a sense voltage, indicative of a load current, and a voltage reference. A control terminal of the power transistor is driven by a first output of the differential amplifier as a function of the detected difference. A voltage clamp circuit coupled to an input terminal generates a floating ground. A short-circuit protection circuit coupled to the floating ground and interposed between a second output of the differential amplifier and the control terminal of the power transistor provides a short-circuit protection for the first output of the differential amplifier. A reaction time circuit is coupled between the first and second outputs of the differential amplifier and a source terminal of the power transistor to limit a short-circuit current at the source terminal.
-
公开(公告)号：US10374600B2
公开(公告)日：2019-08-06
申请号：US16122262
申请日：2018-09-05
IPC分类号： H03K17/284 , H03K5/24 , H03K17/081 , H03K19/20 , H03K3/037 , H03K5/153 , H03K17/08
摘要： First and second comparators receive input signals of opposed polarities and drive operation of a switch in response thereto. A first current generator supplies a first current to the switch which, in response to the control of the first and second comparators, applies the first current, alternatively, to a first node or a second node. A second current generator sinks a second current from the first node and a third current generator sinks a third current from the second node. A logic circuit has inputs coupled to the first node and the second node, respectively, receives respective switching signals having fast switching wavefronts and delayed switching wavefronts. The output of logic circuit is configured for switching between a first state and a second state with switching between the first state and the second state triggered by the fast switching wavefronts of the respective switching signals.
-
公开(公告)号：US20170178744A1
公开(公告)日：2017-06-22
申请号：US15446909
申请日：2017-03-01
CPC分类号： G11C17/18 , G11C11/4125 , G11C17/16 , H03K3/02335 , H03K19/00338 , H03K19/17764
摘要： A radiation hardened memory cell includes an odd number of storage elements configured to redundantly store an input data logic signal. The storage elements include output lines for outputting respective logic signals having respective logic values. A logic combination network receives the respective logic signals and is configured to generate an output signal having a same logic value as a majority of the logic signals output from the storage elements. An exclusive logic sum circuit receives the respective logic signals output from the storage elements and is configured to produce a refresh of the logic data signal as stored in the storage elements when one of the logic signals output from the storage elements undergoes a logic value transition due to an error event.
-
公开(公告)号：US20170011808A1
公开(公告)日：2017-01-12
申请号：US15140023
申请日：2016-04-27
IPC分类号： G11C17/18
CPC分类号： G11C17/18 , G11C11/4125 , G11C17/16 , H03K3/02335 , H03K19/00338 , H03K19/17764
摘要： A radiation hardened memory cell includes an odd number of storage elements configured to redundantly store an input data logic signal. The storage elements include output lines for outputting respective logic signals having respective logic values. A logic combination network receives the respective logic signals and is configured to generate an output signal having a same logic value as a majority of the logic signals output from the storage elements. An exclusive logic sum circuit receives the respective logic signals output from the storage elements and is configured to produce a refresh of the logic data signal as stored in the storage elements when one of the logic signals output from the storage elements undergoes a logic value transition due to an error event.
摘要翻译： 辐射硬化的存储单元包括被配置为冗余地存储输入数据逻辑信号的奇数个存储元件。 存储元件包括用于输出具有各自逻辑值的各个逻辑信号的输出线。 逻辑组合网络接收相应的逻辑信号，并且被配置为产生具有与从存储元件输出的逻辑信号的大部分相同的逻辑值的输出信号。 独占逻辑和电路接收从存储元件输出的相应逻辑信号，并且被配置为当从存储元件输出的逻辑信号之一经历逻辑值转换时，产生存储在存储元件中的逻辑数据信号的刷新 发生错误事件。
-
公开(公告)号：US10547171B2
公开(公告)日：2020-01-28
申请号：US15596465
申请日：2017-05-16
IPC分类号： H02H9/02 , H02H7/00 , H03K17/082
摘要： A power transistor supplying power to a load is coupled to a current limiter circuit including a differential amplifier that operates to detect a difference between a sense voltage, indicative of a load current, and a voltage reference. A control terminal of the power transistor is driven by a first output of the differential amplifier as a function of the detected difference. A voltage clamp circuit coupled to an input terminal generates a floating ground. A short-circuit protection circuit coupled to the floating ground and interposed between a second output of the differential amplifier and the control terminal of the power transistor provides a short-circuit protection for the first output of the differential amplifier. A reaction time circuit is coupled between the first and second outputs of the differential amplifier and a source terminal of the power transistor to limit a short-circuit current at the source terminal.
-
7.发明申请公开(公告)号：US20170141048A1
公开(公告)日：2017-05-18
申请号：US15198877
申请日：2016-06-30
IPC分类号： H01L23/556 , H01L23/29 , H01L23/24 , H01L21/54 , H01L23/552 , H01L23/053
CPC分类号： H01L23/556 , B29C2043/181 , H01L21/54 , H01L23/053 , H01L23/24 , H01L23/296 , H01L23/552 , H01L27/1203 , H01L2224/48091 , H01L2224/73265 , H01L2924/181 , H01L2924/00012 , H01L2924/00014
摘要： A radiation-hard electronic device including a package structure, a semiconductor chip in a cavity within the package structure, an integrated circuit in the semiconductor chip, and structures for protection from radiation for protecting the integrated circuit from ionizing radiation. The structures for protection from radiation include a protective layer of gel, which occupies at least in part the cavity and coats the semiconductor chip.
-
公开(公告)号：US09356587B2
公开(公告)日：2016-05-31
申请号：US14622322
申请日：2015-02-13
CPC分类号： H03K5/125 , H03K5/2436
摘要： A high voltage comparison circuit includes an input stage generating an intermediate signal as a result of a comparison between an input signal and a first voltage reference and an output stage configured to generate an output signal referenced to a second voltage reference (different from the first voltage reference) in response to the intermediate signal.
摘要翻译： 高电压比较电路包括作为输入信号和第一参考电压之间的比较的结果产生中间信号的输入级和被配置为产生参考第二参考电压的输出信号（不同于第一电压 参考）响应于中间信号。
-
公开(公告)号：US10447268B2
公开(公告)日：2019-10-15
申请号：US16112948
申请日：2018-08-27
IPC分类号： H03K19/0185 , H03K3/037 , H03K3/012 , H03K19/00 , H03K3/356 , H03K3/3562 , H03K19/003 , H03K19/20
摘要： A level-shifter circuit operates to shift an input signal referenced to a first set supply voltages to generate an output signal referenced to a second set of supply voltages. The output signal from the level-shifter circuit is latched by a latching circuit. A logic gate has a first input configured to receive the input signal, a second input configured to receive a feedback signal and an output coupled to a input of the level shifting circuit. A feedback circuit has a first input configured to receive the output signal, a second input configured to receive the input signal and an output configured to generate the feedback signal. The feedback circuit operates to sense an uncontrolled switching event of the output signal occurring in the absence of a switching of the input signal and apply, in response thereto, the feedback signal to cancel the uncontrolled switching event.
-
10.发明授权公开(公告)号：US10319686B2
公开(公告)日：2019-06-11
申请号：US15198877
申请日：2016-06-30
IPC分类号： H01L23/552 , H01L23/29 , H01L23/24 , H01L21/54 , H01L23/556 , H01L23/053 , H01L27/12 , B29C43/18
摘要： A radiation-hard electronic device including a package structure, a semiconductor chip in a cavity within the package structure, an integrated circuit in the semiconductor chip, and structures for protection from radiation for protecting the integrated circuit from ionizing radiation. The structures for protection from radiation include a protective layer of gel, which occupies at least in part the cavity and coats the semiconductor chip.
-
-
-
-
-
-
-
-
-
搜索结果
12 条记录 (耗时 0.014 秒)
